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2010 IEEE Computer Society Annual Symposium on VLSI最新文献

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SUT-RNS Forward and Reverse Converters SUT-RNS正向和反向转换器
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1007/978-94-007-1488-5_14
E. Vassalos, D. Bakalis, H. T. Vergos
{"title":"SUT-RNS Forward and Reverse Converters","authors":"E. Vassalos, D. Bakalis, H. T. Vergos","doi":"10.1007/978-94-007-1488-5_14","DOIUrl":"https://doi.org/10.1007/978-94-007-1488-5_14","url":null,"abstract":"","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122970722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pattern-Driven Clock Tree Routing with Via Minimization 通过最小化模式驱动时钟树路由
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.82
A. M. Farhangi, A. Al-Khalili, D. Al-Khalili
{"title":"Pattern-Driven Clock Tree Routing with Via Minimization","authors":"A. M. Farhangi, A. Al-Khalili, D. Al-Khalili","doi":"10.1109/ISVLSI.2010.82","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.82","url":null,"abstract":"Vias have major impact on circuit reliability and manufacturing yield. The variability in via resistance is becoming an increasing concern in nanotechnologies. In this paper a frame work is proposed to construct the clock tree network under via constraint. The number of vias is controlled by considering a pre-specified pattern to route the internal clock tree edges. The impact of the pattern routing is considered in the early phase of clock distribution design phase. We introduce a probabilistic routing demand estimation method to integrate the expected routing demand of the clock net with other clock tree optimization metrics. A new demand driven cost function is exploited in network topology generation as well as branch point embedding stages of a zero skew clock tree algorithm to reduce the number of vias. Our experiments on benchmarks, r1to r5, show reduction of 28% of the total number of vias. The total clock tree wire length is also reduced by an average of 8%. The post-routing induced clock skew is also controlled efficiently, while the number of routing overflows is reduced by more than 70%.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"198 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120869453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Towards Supporting Fault-Tolerance in FPGAs fpga的容错支持
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.99
K. Siozios, D. Soudris, D. Pnevmatikatos
{"title":"Towards Supporting Fault-Tolerance in FPGAs","authors":"K. Siozios, D. Soudris, D. Pnevmatikatos","doi":"10.1109/ISVLSI.2010.99","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.99","url":null,"abstract":"This paper proposes a novel methodology for improving reliability of FPGAs without requiring special purpose hardware. In contrast to related approaches that are applied uniformly over the target architecture, the proposed one insert redundancy only the critical for failure resources. Such an approach leads to reasonable performance improvement.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material 基于双栅材料的传统类mos碳纳米管场效应管性能优化
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.20
Zhou Hailiang, Minxuan Zhang, F. Liang, H. Yue
{"title":"Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material","authors":"Zhou Hailiang, Minxuan Zhang, F. Liang, H. Yue","doi":"10.1109/ISVLSI.2010.20","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.20","url":null,"abstract":"Due to carriers Band-To-Band-Tunneling (BTBT) through channel-source/drain contacts, Conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device design based on dual gate material is proposed. The simulation results show that, with proper choice of tuning gate material, this device design can not only reduce the ambipolar conductance and increase the available ON-OFF current ratio but also decrease the average sub-threshold swing, which are all very desirable in circuit design to reduce the system power and improve the working frequency as well. Further study reveals the fact that the performance of the proposed design depends highly on the choice of tuning gate material which should be paid with much attention in application.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133882517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Scalable Bandwidth Aware Architecture for Connected Component Labeling 一种可扩展的连接组件标记带宽感知体系结构
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.89
V. Kumar, K. Irick, Ahmed Al-Maashri, N. Vijaykrishnan
{"title":"A Scalable Bandwidth Aware Architecture for Connected Component Labeling","authors":"V. Kumar, K. Irick, Ahmed Al-Maashri, N. Vijaykrishnan","doi":"10.1109/ISVLSI.2010.89","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.89","url":null,"abstract":"Recent literature on fast realizations of Connected Component Labeling has proposed single-pass algorithms and architectures that are particularly suited to hardware implementation. These architectures, however, impose input constraints unsuitable for real-time systems that have diverse interface specifications and bandwidth considerations. In this paper we present a streaming Connected Component Labeling architecture that includes a scalable processor that can be tuned to match the I/O bandwidth available in modern embedded computing platforms.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A Floating Gate MOSFET Based Current Reference with Subtraction Technique 基于浮栅MOSFET的电流基准减法技术
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.52
V. Babu, P. Haseena, M. Baiju
{"title":"A Floating Gate MOSFET Based Current Reference with Subtraction Technique","authors":"V. Babu, P. Haseena, M. Baiju","doi":"10.1109/ISVLSI.2010.52","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.52","url":null,"abstract":"In this paper we propose a scheme for generating a reference current which can be implemented in the CMOS technology. The system performance is investigated for a range of supply voltages and temperature. The dependency of CMOS Current reference on supply voltage and temperature is compensated by simply subtracting two current outputs with the same dependencies on the supply voltage and temperature. The system performance is improved by the use of Floating Gate MOSFET. The work includes the mathematical modeling of the proposed current reference circuit and its verification by simulation using TANNAR EDA tools. The layout of the proposed circuit is also prepared. The circuit performance over temperature and supply voltage is better than the prior works in this area. The current reference shows the supply and temperature dependencies of 520 ppm/V and 312 ppm/oC, respectively. The current reference can operate down to 0.9V supply.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129059607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique 利用动态缓冲区分配技术支持多核noc的高效同步
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.16
Xiaowen Chen, Zhonghai Lu, A. Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu
{"title":"Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique","authors":"Xiaowen Chen, Zhonghai Lu, A. Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu","doi":"10.1109/ISVLSI.2010.16","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.16","url":null,"abstract":"This paper explores a dynamic buffer allocation technique to guide a distributed synchronization architecture to support efficient synchronization on multi-core Network-on-Chips (NoCs). The synchronization architecture features two physical buffers to be able to concurrently queue and handle synchronization requests issued by the local processor and remote processors via the on-chip network. Using the dynamic buffer allocation technique, the two physical buffers are dynamically allocated to form multiple virtual buffers in order to improve buffers' utilization. Experiments are carried on to evaluate buffers' utilization.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123604617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Receiver Circuit for Low-Swing Interconnect Schemes 一种用于低摆幅互连方案的接收电路
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.41
Y. Moisiadis, Y. Tsiatouhas
{"title":"A Receiver Circuit for Low-Swing Interconnect Schemes","authors":"Y. Moisiadis, Y. Tsiatouhas","doi":"10.1109/ISVLSI.2010.41","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.41","url":null,"abstract":"This paper presents a new receiver circuit that is suitable for low-swing interconnect schemes in CMOS nanometer technologies. Compared to the conventional receiver, which utilizes a PMOS feedback transistor, the proposed configuration is based on an auxiliary cross-coupled structure, which provides significant reduction of the delay time and eliminates the short circuit current, during transitions. The new receiver outperforms the conventional one, especially when very low power supply voltages are used and large capacitive loads are driven. The proposed topology has been designed in a 90nm CMOS technology and the simulation results confirm that, with respect to the conventional receiver, the delay and energy savings may approach 87% and 60% respectively.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Mesh-Buffer Displacement Optimization Strategy 网格缓冲位移优化策略
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.108
G. Flach, G. Wilke, M. Johann, R. Reis
{"title":"A Mesh-Buffer Displacement Optimization Strategy","authors":"G. Flach, G. Wilke, M. Johann, R. Reis","doi":"10.1109/ISVLSI.2010.108","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.108","url":null,"abstract":"Clock meshes are an important resource for high performance circuit designers due to its robustness to variability. Until recently, there were no tools able to support the use of clock meshes in automated synthesis flows. In the last years commercial tools were adapted to support clock meshes [1]and the academia has addressed the problems of clock mesh design automation and optimization. However, current optimization techniques are still very preliminary. Many other aspects of the clock mesh design can be explored besides of edge removal and buffer placement explored by [2] and [3]. This paper proposes an algorithm to move the mesh buffers over the mesh wires to a position that minimizes the clock skew at the clock sinks. Experimental data show significant skew reduction using the algorithm presented in this paper. The clock mesh area and capacitance are unaffected by this strategy, therefore no overhead is introduced.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127206247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity 电荷恢复电路的体偏置方法:提高能量效率和dpa抗扰性
2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.77
Mehrdad Khatir, A. Ejlali
{"title":"A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity","authors":"Mehrdad Khatir, A. Ejlali","doi":"10.1109/ISVLSI.2010.77","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.77","url":null,"abstract":"Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resistance against differential power analysis attacks (DPA-attacks). Short circuit dissipation and non-adiabatic discharging of capacitance loads are the two major sources of this degradation which are addressed in this paper. In order to reduce these dissipation significantly, we manipulate threshold voltage of circuits transistors by body biasing. To evaluate the efficiency of our method we select a common charge recovery logic called 2N- 2N2P and examine it on 8-bit Brent-Kung adder as well as 4-bit, 8-bit and 16-bit 2N-2N2P carry look-ahead adders. Experimental results show at least 50% reduction in the energy consumption as compared to traditional 2N-2N2P. Moreover, using our technique reduces the dynamic power variation by a factor of 7.8 on the 2N- 2N2P inverter and therefore improves DPA-resistance of charge recovery circuits significantly.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129157005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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