Pattern-Driven Clock Tree Routing with Via Minimization

Vias have major impact on circuit reliability and manufacturing yield. The variability in via resistance is becoming an increasing concern in nanotechnologies. In this paper a frame work is proposed to construct the clock tree network under via constraint. The number of vias is controlled by considering a pre-specified pattern to route the internal clock tree edges. The impact of the pattern routing is considered in the early phase of clock distribution design phase. We introduce a probabilistic routing demand estimation method to integrate the expected routing demand of the clock net with other clock tree optimization metrics. A new demand driven cost function is exploited in network topology generation as well as branch point embedding stages of a zero skew clock tree algorithm to reduce the number of vias. Our experiments on benchmarks, r1to r5, show reduction of 28% of the total number of vias. The total clock tree wire length is also reduced by an average of 8%. The post-routing induced clock skew is also controlled efficiently, while the number of routing overflows is reduced by more than 70%.