2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第5页

Hardware Module Design for Ensuring Trust 保障信任的硬件模块设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.80

A. Fournaris

{"title":"Hardware Module Design for Ensuring Trust","authors":"A. Fournaris","doi":"10.1109/ISVLSI.2010.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.80","url":null,"abstract":"Trust in security demanding software platforms is a very important characteristic. For this reason, Trusted computing group has specified a TPM hardware module that can enforce and guaranty a high trust level to all the platform's involved entities. However, the TPM's features can not be fully exploited in systems under extreme physical conditions. To solve this problem, the use of a special purpose hardware module, physically connected to a host security system's device acting as a local trusted third party, has been proposed. In this paper, we propose a hardware structure of such a hardware module, called Autonomous Attestation Token (AAT) and discuss hardware resource constrains and security bottlenecks that can stem from improper design of its various components. From this analysis it can be concluded that the efficiency of the AAT system is closely related to the efficiency of its public key encryption-decryption unit (RSA encryption-decryption module). Thus, we propose a design methodology toward a low hardware resources (small chip covered area) and side channel attack resistant RSA hardware architecture. This architecture is based on a Fault and Simple power attack resistant version of CRT RSA algorithm that is optimized for the AAT core functionality and hardware structure. To achieve that, Montgomery modular multiplication is used with numbers in carry save format and a Fault and simple power attack resistant modular exponentiation algorithm (FSME) is developed based on this multiplication approach. The hardware structure, realizing the FSME algorithm, is the most complex and resource demanding part of the CRT RSA architecture and its behavior is discussed after implementing it in FPGA technology. The proposed architecture's implementation provides very optimistic results of very low chip covered area and high computation speed thus verifying the efficiency of the proposed algorithms and architecture design approach.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128877562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

European ICT Research: 2011-2012 Outlook for Components and Systems 欧洲ICT研究:2011-2012年组件和系统展望

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.116

P. Tsarchopoulos

引用次数: 1

Logical Core Algorithm: Improving Global Placement 逻辑核心算法:改进全局布局

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.114

Felipe Pinto, L. Cavalheiro, M. Johann, R. Reis

引用次数: 2

Reliability Analysis and Improvement in Nano Scale Design 纳米设计中的可靠性分析与改进

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.48

Mahtab Niknahad, M. Hübner, J. Becker

{"title":"Reliability Analysis and Improvement in Nano Scale Design","authors":"Mahtab Niknahad, M. Hübner, J. Becker","doi":"10.1109/ISVLSI.2010.48","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.48","url":null,"abstract":"According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high fault rates. Most protection methods are based on different redundancy methods which add extra detection and correction features to the design. We strongly believe that in future architectures it become more important assessing the fault tolerance techniques. Having an estimation of system fault tolerance can ensure critical applications working properly. In this work we propose a new method which checks reconfigurable architectures and during runtime finds violent spots in the design for probable transient and permanent failures. This approach is adjustable to either current FPGAs or future nano-architectures which are based on reconfigurability. We define a fault detection model for probable errors which uses an efficient algorithm that proves the fault tolerance in the reconfigurable architecture and computes a reliability factor for the architecture. This helps avoiding using the critical parts by future usages. Our method is applicable to different levels of granularity, such as gate level, logic block level, logic function level, unit level, etc. It is efficient and fast and can be simply integrated into the design flow.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133657753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

System Level Design of Complex Hardware Applications Using ImpulseC 基于impulse的复杂硬件应用系统级设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.10

Georgia Kalogeridou, N. Voros, K. Masselos

引用次数: 4

Performance Analysis of 3D NoCs Partitioning Methods 三维noc划分方法的性能分析

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.26

M. Ebrahimi, M. Daneshtalab, P. Liljeberg, H. Tenhunen

引用次数: 4

Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture 小世界:未来SoC架构中noc的动态

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.112

M. Coppola

引用次数: 0

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures 系统探索高能效应用的片上网络架构

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.60

Iasonas Filippopoulos, Iraklis Anagnostopoulos, A. Bartzas, D. Soudris, G. Economakos

引用次数: 5

Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model 基于延迟感知模型的异步片上网络精确仿真

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.45

N. Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, T. Hanyu

{"title":"Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model","authors":"N. Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, T. Hanyu","doi":"10.1109/ISVLSI.2010.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.45","url":null,"abstract":"A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this ”delay-aware” model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spider on NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs 基于仿真的3D集成电路无线射频互连可行性研究

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.33

A. More, B. Taskin

引用次数: 7