2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第4页

Efficient Hardware Looping Units for FPGAs fpga的高效硬件环路单元

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.63

N. Kavvadias, K. Masselos

{"title":"Efficient Hardware Looping Units for FPGAs","authors":"N. Kavvadias, K. Masselos","doi":"10.1109/ISVLSI.2010.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.63","url":null,"abstract":"Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead loop controllers applicable to perfect loop nests operating on multi-dimensional data is presented. The design of such loop controllers is formalized by the introduction of a hardware algorithm that fully automates this task for the spectrum of behavioral as well as generated register-transfer level architectures. The presented algorithm would prove beneficial in the field of high-level synthesis of architectures for data-intensive processing. It is also shown that the proposed loop controllers can be efficiently utilized for supporting generalized loop structures such as imperfect loop nests. The performance characteristics (cycle time, chip area) of the proposed architectures have been evaluated for FPGA target implementations. It is shown that maximum clock frequencies of above 230MHz with low logic footprints of about 1.4% of the overall logic resources can be achieved for supporting up to 8 nested loops with 16-bit indices on a modestly-sized Xilinx Virtex-5 device.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":" 872","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters 面积节约型换桶器布局的生成与探索

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.73

Alen Bardizbanyan, K. Subramaniyan, P. Larsson-Edefors

{"title":"Generation and Exploration of Layouts for Area-Efficient Barrel Shifters","authors":"Alen Bardizbanyan, K. Subramaniyan, P. Larsson-Edefors","doi":"10.1109/ISVLSI.2010.73","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.73","url":null,"abstract":"Good layout quality is very important in order to obtain efficient integrated circuits, and custom design methods are thus considered when speed, power, and area requirements are very strict. But since custom design styles require extensive and specialized development resources, automated, less optimal design methods are often chosen. Alternate methods to create efficient layouts may prove useful, especially since custom layout in future technology nodes is associated with prohibitive nonrecurring engineering (NRE) costs. The prototype layout generation environment shown in this paper allows us to define, evaluate and modify fine-grained cell placement strategies for barrel shifters in a quick manner. The three different 90-nm shifter circuit implementations demonstrated here show a performance that is on par with circuits harnessing the capabilities offered by conventional tools. Furthermore, this performance is achieved using the least possible die area. For example, a 32-bit fan-out split shifter conventionally laid out and clocked at 1.11 GHz, dissipates 0.37 mW of switching power and occupies an area of 5698 μm2. The same shifter circuit placed using our environment and routed conventionally, equivalently dissipates 0.34 mW, but occupies only 4711 μm2.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications 安全关键应用中片上冗余的安全感知位置和路由

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.51

Romuald Girardey, M. Hübner, J. Becker

引用次数: 7

Memory-Less Pipeline Dynamic Circuit Design Technique 无内存管道动态电路设计技术

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.42

T. Haniotakis, Zaher Owda, Y. Tsiatouhas

{"title":"Memory-Less Pipeline Dynamic Circuit Design Technique","authors":"T. Haniotakis, Zaher Owda, Y. Tsiatouhas","doi":"10.1109/ISVLSI.2010.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.42","url":null,"abstract":"A desirable characteristic of VLSI circuits is high speed operation. The use of dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. Another common design technique in order to achieve high operating speed is the use of pipeline schemes. However, the higher the required operating frequency, the higher the number of stages we must implement in the pipeline. In addition, a limiting factor in cases with a large number of stages, are the restrictions imposed from the required memory elements. These memory elements not only increase the silicon area of the implementation but also restrict the maximum achievable frequency due to their internal delays. In this paper, we propose a memory-less pipeline design style, where the combinational part is implemented with dynamic circuits that offer the desirable high speed operation while the memory elements are eliminated due to an intelligent clocking scheme. Thus, the proposed design technique provides the advantage of high performance operation and at the same time compares favorably to preexisting approaches with respect to silicon overhead and power requirements.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology 90nm CMOS多电压耐辐射带隙基准电路的设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.64

E. Vilella, Á. Diéguez

引用次数: 2

Side Channel Attacks Cryptanalysis against Block Ciphers Based on FPGA Devices 基于FPGA的分组密码侧信道攻击密码分析

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.104

A. Bechtsoudis, N. Sklavos

引用次数: 19

Reliability-Aware Dynamic Voltage and Frequency Scaling 可靠性感知的动态电压和频率缩放

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.54

F. Firouzi, M. Salehi, Fan Wang, S. M. Fakhraie, S. Safari

引用次数: 9

Reconfigurable Architectures for Bioinformatics Applications 生物信息学应用的可重构架构

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.111

A. Dollas

引用次数: 1

The SATURN Approach to SysML-Based HW/SW Codesign 基于sysml的硬件/软件协同设计的SATURN方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.95

W. Müller, Da He, Fabian Mischkalla, Arthur Wegele, P. Whiston, P. Peñil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, Manuel Carballeda

引用次数: 28

A BDD-Based Design of an Area-Power Efficient Asynchronous Adder 基于bdd的区域节能异步加法器设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.47

G. Paul, R. Reddy, C. Mandal, B. Bhattacharya

引用次数: 5