2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第3页

Autonomous Design in VLSI: Growing and Learning on Silicon VLSI中的自主设计:在硅上的成长与学习

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.109

L. Krundel, D. Mulvaney, V. Chouliaras

引用次数: 0

Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA 用于FPGA安全关键应用的混合信号多冗余系统

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.11

Romuald Girardey, M. Hübner, J. Becker

引用次数: 1

A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC 基于CRT和MRC的增强模集{2n- 1,2n + 1,22n, 22n+1-1}的反向变换器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.105

A. S. Molahosseini, K. Navi

引用次数: 24

Bitstream Efficiency of Field Programmable One-Hot Arrays 现场可编程单热阵列的比特流效率

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.117

M. Arnold, P. Vouzis, Jung H. Cho

引用次数: 1

A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor Circuits 一种用于生物医学传感器电路的低功耗FSK调制器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.74

K. Zhu, M. Haider, S. Yuan, S. Islam

{"title":"A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor Circuits","authors":"K. Zhu, M. Haider, S. Yuan, S. Islam","doi":"10.1109/ISVLSI.2010.74","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.74","url":null,"abstract":"Low-power wireless telemetry is extremely important for non-invasive monitoring of biomedical sensor signals. Usually for successful monitor of various physiological parameters, an implantable sensor incorporates a transmitter unit to send the sensor data outside of the human body for further diagnostics. This paper reports a new low-power frequency shift keying (FSK) modulator for a biomedical sensor circuits. With a very simple architecture, this circuit integrates the modulation functionality into the oscillator itself by using the data signal to control the oscillation frequency. Besides, it can generate tunable carrier frequencies for different data signals. The carrier frequency can range from 5 MHz to tens of MHz with configurable tuning for adaptable data rate applications. In addition, the data rate from 450kbps to several Mbps can be achieved for common applications. The modulator is implemented in a 0.35 μm bulk-CMOS process with a power supply voltage of 2.5 V. For a carrier frequency of 10MHz the entire unit consumes less than 1 μA current which makes the design very suitable for low-power biomedical application. The circuit has already been submitted for monolithic integration.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130020981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques 验证代码运动技术的数据流驱动的等价性检查

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.58

C. Karfa, D. Sarkar, C. Mandal

{"title":"Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques","authors":"C. Karfa, D. Sarkar, C. Mandal","doi":"10.1109/ISVLSI.2010.58","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.58","url":null,"abstract":"Code motion techniques are extensively used in the pre-synthesis optimization and the scheduling phases of high-level synthesis (HLS) of digital circuits for control intensive behaviours. A formal verification method for checking correctness of code motion techniques is presented in this paper. Finite state machine with datapath (FSMD) models have been used to represent the input and the output behaviours of each synthesis step. The method consists in introducing cut points in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD, the process is then repeated with the FSMDs interchanged. It has been underlined in this work that for non-uniform code motions, identifying equivalent path segment involves model checking of specific data-flow driven properties. Unlike many other reported techniques, the method is capable of verifying both uniform and non-uniform code motion techniques. The method is tested on the synthesis results of a high-level synthesis tool called SPARK for several HLS benchmarks. Experimental results demonstrate the effectiveness of the method.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network 2D-Mesh网络中双周期NoC路由器的时延模型

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.22

Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang

引用次数: 2

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures 延迟区优化粗粒度可重构协处理器体系结构的高级综合方法

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.8

S. Xydis, K. Pekmestzi, D. Soudris, G. Economakos

{"title":"High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures","authors":"S. Xydis, K. Pekmestzi, D. Soudris, G. Economakos","doi":"10.1109/ISVLSI.2010.8","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.8","url":null,"abstract":"As Very Large Scale Integration (VLSI) process technology continues to scale down transistor sizes, modern computing devices are becoming extremely complex. In order to face this complexity explosion, the shifting of design methodologies towards higher level of abstraction has been proposed. This high level view of the design procedure enables the automated synthesis of applications’ architecture that is written in an application-level description i.e. C/C++. Additionally, it allows designers to explore the tradeoffs between different system and implementation parameters to conclude in an efficient design solution. The work done during this PhD thesis targets the exploration and optimization of the design solutions in a global manner, by focusing on the combined development of novel (i) system-level automated design methodologies/tools and (ii) circuit-level techniques for a specific class of system architectures - reconfigurable systems. Reconfigurable Computing has been proposed as a new paradigm to address the conflicting design requirements for high performance and area efficiency. Towards this direction, fine- and coarse-grained reconfigurable coprocessor architectures have been presented. Unlike fine-grained, coarse-grained architectures (CGA) operate at the word level of granularity exhibiting better power and performance features, close to ASIC solutions [1]. However, a performance-area-power gap still exists for CGAs to overcome ASIC implementations [2]. Thus, new fundamental design problems/questions has been raised. Does this gap be a bridgeable one? How can CGAs shift even closer to ASIC datapaths? In order to address the aforementioned problems, we identified that hardware sharing at the bit-level generates CGAs with performance and area characteristics closer to ASICs than the existing ones. Thus, this thesis proposes new architectural templates and the corresponding high level synthesis methodologies to enable a new shifting on the state-of-the-art of CGAs.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129207267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation 用于早期内存层次评估的可扩展内存模拟器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.106

Theodoros Lioris, G. Dimitroulakos, K. Masselos

{"title":"XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation","authors":"Theodoros Lioris, G. Dimitroulakos, K. Masselos","doi":"10.1109/ISVLSI.2010.106","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.106","url":null,"abstract":"This paper presents a memory hierarchy evaluation framework for multimedia applications. It takes as input a high level C code application description and a memory hierarchy specification and provides statistics characterizing the memory operation. Essentially the tool is a specialized C++ data type library which is used to replace the application's data types with others that monitor memory access activity. XMSIM's operation is event driven which means that every access to a specific data structure is converted to a message towards the memory model which subsequently emulates memory hierarchy operation. The memory model is highly parametric allowing a large number of alternatives to be modeled. XMSIM's main advantage is its modularity allowing the designer to alter specific aspects of the memory operation beyond the predefined ones. The main features are the capability to: 1) simulate any subset of the application's data types, 2) user defined mapping of data to memories, 3) simultaneously simulate multiple memory hierarchy scenarios, 4) immediate feedback to code transformations effect on memory hierarchy behavior, 5) verification utilities for the validation of code transformations.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116783403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair 基于多操作微码的内存故障检测与修复内置自检建模与仿真

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.88

R. K. Sharma, A. Sood

引用次数: 8