2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第3页

Autonomous Design in VLSI: Growing and Learning on Silicon VLSI中的自主设计:在硅上的成长与学习

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.109

L. Krundel, D. Mulvaney, V. Chouliaras

引用次数: 0

A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC 基于CRT和MRC的增强模集{2n- 1,2n + 1,22n, 22n+1-1}的反向变换器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.105

A. S. Molahosseini, K. Navi

引用次数: 24

Bitstream Efficiency of Field Programmable One-Hot Arrays 现场可编程单热阵列的比特流效率

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.117

M. Arnold, P. Vouzis, Jung H. Cho

引用次数: 1

Efficient Hardware Looping Units for FPGAs fpga的高效硬件环路单元

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.63

N. Kavvadias, K. Masselos

{"title":"Efficient Hardware Looping Units for FPGAs","authors":"N. Kavvadias, K. Masselos","doi":"10.1109/ISVLSI.2010.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.63","url":null,"abstract":"Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead loop controllers applicable to perfect loop nests operating on multi-dimensional data is presented. The design of such loop controllers is formalized by the introduction of a hardware algorithm that fully automates this task for the spectrum of behavioral as well as generated register-transfer level architectures. The presented algorithm would prove beneficial in the field of high-level synthesis of architectures for data-intensive processing. It is also shown that the proposed loop controllers can be efficiently utilized for supporting generalized loop structures such as imperfect loop nests. The performance characteristics (cycle time, chip area) of the proposed architectures have been evaluated for FPGA target implementations. It is shown that maximum clock frequencies of above 230MHz with low logic footprints of about 1.4% of the overall logic resources can be achieved for supporting up to 8 nested loops with 16-bit indices on a modestly-sized Xilinx Virtex-5 device.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":" 872","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131977923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair 基于多操作微码的内存故障检测与修复内置自检建模与仿真

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.88

R. K. Sharma, A. Sood

引用次数: 8

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters 面积节约型换桶器布局的生成与探索

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.73

Alen Bardizbanyan, K. Subramaniyan, P. Larsson-Edefors

{"title":"Generation and Exploration of Layouts for Area-Efficient Barrel Shifters","authors":"Alen Bardizbanyan, K. Subramaniyan, P. Larsson-Edefors","doi":"10.1109/ISVLSI.2010.73","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.73","url":null,"abstract":"Good layout quality is very important in order to obtain efficient integrated circuits, and custom design methods are thus considered when speed, power, and area requirements are very strict. But since custom design styles require extensive and specialized development resources, automated, less optimal design methods are often chosen. Alternate methods to create efficient layouts may prove useful, especially since custom layout in future technology nodes is associated with prohibitive nonrecurring engineering (NRE) costs. The prototype layout generation environment shown in this paper allows us to define, evaluate and modify fine-grained cell placement strategies for barrel shifters in a quick manner. The three different 90-nm shifter circuit implementations demonstrated here show a performance that is on par with circuits harnessing the capabilities offered by conventional tools. Furthermore, this performance is achieved using the least possible die area. For example, a 32-bit fan-out split shifter conventionally laid out and clocked at 1.11 GHz, dissipates 0.37 mW of switching power and occupies an area of 5698 μm2. The same shifter circuit placed using our environment and routed conventionally, equivalently dissipates 0.34 mW, but occupies only 4711 μm2.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network 2D-Mesh网络中双周期NoC路由器的时延模型

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.22

Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang

引用次数: 2

XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation 用于早期内存层次评估的可扩展内存模拟器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.106

Theodoros Lioris, G. Dimitroulakos, K. Masselos

{"title":"XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation","authors":"Theodoros Lioris, G. Dimitroulakos, K. Masselos","doi":"10.1109/ISVLSI.2010.106","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.106","url":null,"abstract":"This paper presents a memory hierarchy evaluation framework for multimedia applications. It takes as input a high level C code application description and a memory hierarchy specification and provides statistics characterizing the memory operation. Essentially the tool is a specialized C++ data type library which is used to replace the application's data types with others that monitor memory access activity. XMSIM's operation is event driven which means that every access to a specific data structure is converted to a message towards the memory model which subsequently emulates memory hierarchy operation. The memory model is highly parametric allowing a large number of alternatives to be modeled. XMSIM's main advantage is its modularity allowing the designer to alter specific aspects of the memory operation beyond the predefined ones. The main features are the capability to: 1) simulate any subset of the application's data types, 2) user defined mapping of data to memories, 3) simultaneously simulate multiple memory hierarchy scenarios, 4) immediate feedback to code transformations effect on memory hierarchy behavior, 5) verification utilities for the validation of code transformations.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116783403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA 用于FPGA安全关键应用的混合信号多冗余系统

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.11

Romuald Girardey, M. Hübner, J. Becker

引用次数: 1

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques 验证代码运动技术的数据流驱动的等价性检查

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.58

C. Karfa, D. Sarkar, C. Mandal

{"title":"Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques","authors":"C. Karfa, D. Sarkar, C. Mandal","doi":"10.1109/ISVLSI.2010.58","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.58","url":null,"abstract":"Code motion techniques are extensively used in the pre-synthesis optimization and the scheduling phases of high-level synthesis (HLS) of digital circuits for control intensive behaviours. A formal verification method for checking correctness of code motion techniques is presented in this paper. Finite state machine with datapath (FSMD) models have been used to represent the input and the output behaviours of each synthesis step. The method consists in introducing cut points in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints, and identifying equivalent finite path segments in the other FSMD, the process is then repeated with the FSMDs interchanged. It has been underlined in this work that for non-uniform code motions, identifying equivalent path segment involves model checking of specific data-flow driven properties. Unlike many other reported techniques, the method is capable of verifying both uniform and non-uniform code motion techniques. The method is tested on the synthesis results of a high-level synthesis tool called SPARK for several HLS benchmarks. Experimental results demonstrate the effectiveness of the method.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129228958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3