2010 IEEE Computer Society Annual Symposium on VLSI最新文献_第2页

Design Automation and Analysis of Resonant Rotary Clocking Technology 谐振旋转时钟技术的设计、自动化与分析

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.28

V. Honkote

引用次数: 4

Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs 从控制密集型顺序程序中自动生成大规模并行硬件

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.40

Michael F. Dossis

{"title":"Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs","authors":"Michael F. Dossis","doi":"10.1109/ISVLSI.2010.40","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.40","url":null,"abstract":"High-level synthesis has been envisaged as a suitable methodology to design and deliver on time, at least large parts of today’s complex IC systems. This paper describes a unified and integrated HLS framework, to automatically produce custom and massively-parallel hardware, including its memory and system interfaces from high-level sequential program code. Using compiler-generators and logic programming techniques, provably-correct hardware compilation flow is achieved. The utilized hardware optimization inference engine is driven by a set of resource constraints, which limit to a certain boundary the number of available hardware operators to function in parallel during each control step. This optimization reduces drastically the number of different control steps (states) of the implemented application. The hardware compilation runs are completed in orders-of-magnitude less time than that which would be needed by even very experienced HDL designers to implement the same applications in RTL code. Implementation results from synthesis of a number of control-dominated, linear and repetitive, applications including a MPEG video compression engine with up to a few hundred states, are presented. In all cases the HLS framework delivers quickly provably-correct, implementable RTL code and the optimized schedule is reduced at up to 30% in comparison with the initial schedule.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS 一种低功耗、高性能阈值逻辑的65nm CMOS标准电池倍增器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.32

S. Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, S. Vrudhula

引用次数: 3

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures MULTICUBE:多核架构的多目标设计空间探索

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1007/978-94-007-1488-5_4

C. Silvano, W. Fornaciari, G. Palermo, V. Zaccaria, F. Castro, Marcos Martínez, S. Bocchio, R. Zafalon, P. Avasare, G. Vanmeerbeeck, C. Ykman-Couvreur, M. Wouters, C. Kavka, L. Onesti, A. Turco, U. Bondi, Giovanni Mariani, H. Posadas, E. Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang

引用次数: 81

Low Power Single Electron Or/Nor Gate Operating at 10GHz 低功耗单电子或/或门工作在10GHz

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.78

T. Tsiolakis, G. Alexiou, Nikos Konofaos

引用次数: 5

Improved Yield in Nanotechnology Circuits Using Non-square Meshes 利用非方形网格提高纳米电路成品率

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.113

C. Argyrides, Nikolaos Mavrogiannakis, D. Pradhan

{"title":"Improved Yield in Nanotechnology Circuits Using Non-square Meshes","authors":"C. Argyrides, Nikolaos Mavrogiannakis, D. Pradhan","doi":"10.1109/ISVLSI.2010.113","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.113","url":null,"abstract":"Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected to have high defect density and have be handled with effective defect tolerant techniques. In this paper, we propose a technique, which for a given circuit size, utilizes different combinations of defect-free non-square but rectangular crossbars to construct the desired circuit with improved yield. We extend our recently proposed algorithm[1] to cope with non-square meshes. We aim to improve the number of defect-free crossbars and also to improve the total yield by connecting defect-free non-square but rectangular subsets together. We also estimate the reliability of the resulting circuits and observed that while the yield increases significantly in our architecture, the reliability, however, decreases due to the increased number of interconnects. Finally, we provide a guideline to optimize the architecture making an optimal trade off between the yield and the reliability.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129708566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support LE1:支持硬件pthread的可参数化VLIW芯片多处理器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.107

D. Stevens, V. Chouliaras

{"title":"LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support","authors":"D. Stevens, V. Chouliaras","doi":"10.1109/ISVLSI.2010.107","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.107","url":null,"abstract":"We discuss LE1, a parameterized VLIW Chip Multiprocessor (CMP) adhering to the shared memory programmers model. LE1's novelty lies in its ability to perform dynamic thread-spawning through hardware support for PThread-like primitives in addition to its substantial architectural and microarchitectural parameterization. Dynamic (hardware) thread creation is very fast and removes the need for an executive/OS, presenting to the application programmer a 'bare-metal' multiprocessor, capable of exploiting all forms of parallelism. The core LE1 CPU is a configurable, 8-stage pipeline VLIW engine with a proprietary Instruction Set Architecture (ISA) supporting both partial and full predication and pipelined, multi-input, multi-output (MIMO) instruction extensions. The LE1 CMP is parameterizable as to the number of processors, their issue capability, internal microarchitectural features, functional unit mix and latency and the local memory system architecture. Preliminary results indicate near-linear performance improvement when executing a threaded version of the Mandelbrot calculation on 2-way and 4-way processor configurations with a 256 KB, 4-way banked tightly-coupled memory system. Similar trends are seen when executing a threaded matrix multiplication benchmark. We present these findings along with VLSI implementations of 4-way, dual-issue and 3-way, quad issue multiprocessor configurations.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128643088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT 结合扫描压缩、分区链和RPCT的层次DFT

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.59

P. Srinivasan, R. Farrell

引用次数: 6

Clock Tree Synthesis with XOR Gates for Polarity Assignment 时钟树合成与异或门极性分配

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.62

Jianchao Lu, B. Taskin

引用次数: 10

ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters 可重构模数转换器自适应控制单元的ASIC设计

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI: 10.1109/ISVLSI.2010.79

Z. Razak, A. Erdogan, T. Arslan

{"title":"ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters","authors":"Z. Razak, A. Erdogan, T. Arslan","doi":"10.1109/ISVLSI.2010.79","DOIUrl":"https://doi.org/10.1109/ISVLSI.2010.79","url":null,"abstract":"There is a need to use a truly adaptive analog-to-digital converter (ADC) to respond to any signal change and reduce the power consumption with less implementation complexity. The paper presents a front-end ASIC implementation for an adaptive control unit (ACU) for a reconfigurable ADC. The control unit is based on an adaptive algorithm that changes either the converter resolution or sampling-rate within an observation interval. Switching activity on the digital ADC output is monitored, evaluated and compared to threshold values. The resolution (or sampling-rate) is increased when the switching activity is high and decreased when the activity is low. Since the adaptive control unit is simple, it is suitable for most Nyquist-rate ADCs especially for area-limited portable devices. The module is synthesized using AMS 0.35μm/3.3V CMOS standard libraries. In adaptive resolution ADC application, the ACU occupies only 677 equivalent 2-input NAND gates and consumes only 1.01mW. Meanwhile, for adaptive sampling-rate ADC, the gate density is 703 and power consumption is 2.22mW. The results show that the area complexity of the ACU is small and consumes minimum power. For this reason, the ACU is suitable for adaptive ADC implementation targeting low power wireless applications.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116129201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3