Improved Yield in Nanotechnology Circuits Using Non-square Meshes

Abstract

Nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires has been predicted to be an alternative to silicon technology since lithography based IC is approaching its limit in terms of feature size. However, such processes are expected to have high defect density and have be handled with effective defect tolerant techniques. In this paper, we propose a technique, which for a given circuit size, utilizes different combinations of defect-free non-square but rectangular crossbars to construct the desired circuit with improved yield. We extend our recently proposed algorithm[1] to cope with non-square meshes. We aim to improve the number of defect-free crossbars and also to improve the total yield by connecting defect-free non-square but rectangular subsets together. We also estimate the reliability of the resulting circuits and observed that while the yield increases significantly in our architecture, the reliability, however, decreases due to the increased number of interconnects. Finally, we provide a guideline to optimize the architecture making an optimal trade off between the yield and the reliability.