Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI:10.1109/ISVLSI.2010.71

B. Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, J. Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, Andreas Wiefrink, B. Vanthournout, Philippe Martin

{"title":"Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach","authors":"B. Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, S. Xydis, A. Bartzas, D. Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, A. Hemani, A. Jantsch, G. Vanmeerbeeck, J. Kreku, Kari Tiensyrjä, F. Ieromnimon, D. Kritharidis, Andreas Wiefrink, B. Vanthournout, Philippe Martin","doi":"10.1109/ISVLSI.2010.71","DOIUrl":null,"url":null,"abstract":"The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2010.71","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

Abstract

The project will address two main challenges of prevailing architectures: 1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption, 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure, 2) Developing tool support for parallelizing and mapping application son the multi-core target platform and customizing the processing cores for the application.

查看原文本刊更多论文

可扩展多核架构的映射优化:MOSART方法

该项目将解决当前架构的两个主要挑战:1)由于单个全局共享内存具有高访问时间和功耗而导致的全球互连和内存瓶颈;2)编程异构多核平台的困难，特别是在动态管理分布式内存中的数据结构方面。MOSART旨在通过具有分布式存储器组织的多核架构，片上网络(NoC)通信骨干和可配置的处理核心来克服这些问题，这些核心可以扩展，优化和定制，以实现不同类型应用的不同能源，性能，成本和尺寸要求。MOSART通过以下方式实现:1)为管理抽象数据结构提供平台支持，包括中间件服务和基于NoC的通信基础设施的运行时数据管理器;2)开发工具支持在多核目标平台上并行化和映射应用程序，并为应用程序定制处理核心。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2010 IEEE Computer Society Annual Symposium on VLSI

自引率

0.00%

发文量