3-D集成电路的高性能TSV架构

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI:10.1109/ISVLSI.2010.24

M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, H. Tenhunen

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引用次数: 4

摘要

三维集成电路(3d -d ic)在性能、封装密度、互连功耗和功能方面都优于传统的平面集成电路。由于采用硅通孔(tsv)的三维集成电路的性能取决于垂直层间互连，因此本文提出了一种用于tsv的高性能总线架构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High-Performance TSV Architecture for 3-D ICs

Three-dimensional integrated circuits (3-D ICs) outperform traditional planar ICs in terms of performance, packaging density, interconnection power consumption, and functionality. Since the performance of 3-D ICs employing Through Silicon Vias (TSVs) depends on vertical interlayer interconnects, in this paper we present a high-performance bus architecture for TSVs.

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来源期刊

2010 IEEE Computer Society Annual Symposium on VLSI

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