一类面积-时间有效模2n+1加法器

2010 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2010-07-05 DOI:10.1109/ISVLSI.2010.35

H. T. Vergos

{"title":"一类面积-时间有效模2n+1加法器","authors":"H. T. Vergos","doi":"10.1109/ISVLSI.2010.35","DOIUrl":null,"url":null,"abstract":"A family of diminished-1 modulo $2^n+1$ adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in $\\log_2n$ prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A Family of Area-Time Efficient Modulo 2n+1 Adders\",\"authors\":\"H. T. Vergos\",\"doi\":\"10.1109/ISVLSI.2010.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A family of diminished-1 modulo $2^n+1$ adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in $\\\\log_2n$ prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.\",\"PeriodicalId\":187530,\"journal\":{\"name\":\"2010 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2010.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2010.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

本文提出了一类消-1模$2^n+1$加法器。家族的所有成员都使用一个稀疏进位计算单元来推导$\log_2n$前缀级别中的一些进位，而其余的所有进位都在一个额外的级别中计算。与之前的方案相比，提议的加法器提供了显著的面积和功耗节约，同时保持了高运行速度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Family of Area-Time Efficient Modulo 2n+1 Adders

A family of diminished-1 modulo $2^n+1$ adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in $\log_2n$ prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.

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2010 IEEE Computer Society Annual Symposium on VLSI

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