A Family of Area-Time Efficient Modulo 2n+1 Adders

Abstract

A family of diminished-1 modulo $2^n+1$ adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in $\log_2n$ prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.