{"title":"一种新型低功耗软容错SRAM单元","authors":"N. Axelos, K. Pekmestzi, N. Moschopoulos","doi":"10.1109/ISVLSI.2010.83","DOIUrl":null,"url":null,"abstract":"In this paper we present a new 12T loadless SRAM cell that exhibits soft error resilience characteristics. The proposed cell is based on an interlocked structure with guard gates that provides an x80 increase in soft error resilience compared to a typical unprotected 6T SRAM cell, while addressing the static power consumption issue of modern CMOS technologies. At a 90nm technology, simulations show that the investigated 12T SRAM cell draws 3 times less leakage current than a DICE cell of similarly sized transistors and 20% less than a typical 6T cell.","PeriodicalId":187530,"journal":{"name":"2010 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A New Low-Power Soft-Error Tolerant SRAM Cell\",\"authors\":\"N. Axelos, K. Pekmestzi, N. Moschopoulos\",\"doi\":\"10.1109/ISVLSI.2010.83\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a new 12T loadless SRAM cell that exhibits soft error resilience characteristics. The proposed cell is based on an interlocked structure with guard gates that provides an x80 increase in soft error resilience compared to a typical unprotected 6T SRAM cell, while addressing the static power consumption issue of modern CMOS technologies. At a 90nm technology, simulations show that the investigated 12T SRAM cell draws 3 times less leakage current than a DICE cell of similarly sized transistors and 20% less than a typical 6T cell.\",\"PeriodicalId\":187530,\"journal\":{\"name\":\"2010 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2010.83\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2010.83","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we present a new 12T loadless SRAM cell that exhibits soft error resilience characteristics. The proposed cell is based on an interlocked structure with guard gates that provides an x80 increase in soft error resilience compared to a typical unprotected 6T SRAM cell, while addressing the static power consumption issue of modern CMOS technologies. At a 90nm technology, simulations show that the investigated 12T SRAM cell draws 3 times less leakage current than a DICE cell of similarly sized transistors and 20% less than a typical 6T cell.
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