2016 IEEE International Electron Devices Meeting (IEDM)最新文献

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FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin FOI FinFET具有超低寄生电阻,在隔离体翅片上形成全金属源极和漏极
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838438
Qingzhu Zhang, H. Yin, Jun Luo, Hong Yang, Lingkuan Meng, Yudong Li, Zhenhua Wu, Yanbo Zhang, Yongkui Zhang, Changliang Qin, Junjie Li, Jianfeng Gao, Guilei Wang, W. Xiong, J. Xiang, Zhangyu Zhou, S. Mao, Gaobo Xu, Jinbiao Liu, Y. Qu, Tao Yang, Junfeng Li, Qiuxia Xu, Jiang Yan, Huilong Zhu, Chao Zhao, Tianchun Ye
{"title":"FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin","authors":"Qingzhu Zhang, H. Yin, Jun Luo, Hong Yang, Lingkuan Meng, Yudong Li, Zhenhua Wu, Yanbo Zhang, Yongkui Zhang, Changliang Qin, Junjie Li, Jianfeng Gao, Guilei Wang, W. Xiong, J. Xiang, Zhangyu Zhou, S. Mao, Gaobo Xu, Jinbiao Liu, Y. Qu, Tao Yang, Junfeng Li, Qiuxia Xu, Jiang Yan, Huilong Zhu, Chao Zhao, Tianchun Ye","doi":"10.1109/IEDM.2016.7838438","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838438","url":null,"abstract":"The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123785726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Resonant-tunneling-diode terahertz oscillators and applications 共振隧道二极管太赫兹振荡器及其应用
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838504
M. Asada, S. Suzuki
{"title":"Resonant-tunneling-diode terahertz oscillators and applications","authors":"M. Asada, S. Suzuki","doi":"10.1109/IEDM.2016.7838504","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838504","url":null,"abstract":"We report on our recent results of resonant tunneling diodes oscillating in the terahertz frequency range, including the structures for high frequency oscillation up to 1.92 THz at room temperature, high output power, high-speed direct modulation for wireless communication, and frequency tenability for spectroscopy.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130486730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Carbon nanotube complementary logic with low-temperature processed end-bonded metal contacts 具有低温加工末端键合金属触点的碳纳米管互补逻辑
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838350
Jianshi Tang, Q. Cao, D. Farmer, G. Tulevski, Shu-Jen Han
{"title":"Carbon nanotube complementary logic with low-temperature processed end-bonded metal contacts","authors":"Jianshi Tang, Q. Cao, D. Farmer, G. Tulevski, Shu-Jen Han","doi":"10.1109/IEDM.2016.7838350","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838350","url":null,"abstract":"CNT-based complementary logic using low-temperature processed end-boned metal contacts are demonstrated. This new form of end-bonded contact is made by carbon dissolution into metal contacts with high carbon solubility (e.g., Ni and Co), which requires only low annealing temperature (400−600 °C). As-fabricated end-bonded Ni contacts serve as robust p-type contacts to CNTs and perform better than standard Pd side-bonded contacts at scaled dimensions. In addition, stable NFETs are converted from PFETs using Al2O3 as an n-type physicochemical doping layer. CMOS inverters are further built with end-bonded contacts for both PFETs and NFETs, featuring the smallest contact size thus far for CNT inverters. These new findings could pave the way to realizing CNT-based scalable CMOS technology.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"52 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122107985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Comprehensive model for progressive breakdown in nFETs and pFETs nfet和pfet渐进击穿的综合模型
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838522
S. Lombardo, E. Wu, J. Stathis
{"title":"Comprehensive model for progressive breakdown in nFETs and pFETs","authors":"S. Lombardo, E. Wu, J. Stathis","doi":"10.1109/IEDM.2016.7838522","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838522","url":null,"abstract":"Through comparison with a large data set, we show that progressive breakdown (PBD) of gate oxides is described by a physical model coupling carrier energy dissipation to electromigration producing the PBD growth. Dependence on temperature, voltage, carrier type, oxide thickness, and the statistics are well described in a consistent framework.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications 22nm FDSOI技术,适用于新兴的移动、物联网和射频应用
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/iedm.2016.7838029
R. Carter, J. Mazurier, L. Pirro, J.-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet, J. Schaeffer, B. Rice
{"title":"22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications","authors":"R. Carter, J. Mazurier, L. Pirro, J.-U. Sachse, P. Baars, J. Faul, C. Grass, G. Grasshoff, P. Javorka, T. Kammler, A. Preusse, S. Nielsen, T. Heller, J. Schmidt, H. Niebojewski, P. Chou, E. Smith, E. Erben, C. Metze, C. Bao, Y. Andee, I. Aydin, S. Morvan, J. Bernard, E. Bourjot, T. Feudel, D. Harame, R. Nelluri, H.-J. Thees, L. M-Meskamp, J. Kluth, R. Mulfinger, M. Rashed, R. Taylor, C. Weintraub, J. Hoentschel, M. Vinet, J. Schaeffer, B. Rice","doi":"10.1109/iedm.2016.7838029","DOIUrl":"https://doi.org/10.1109/iedm.2016.7838029","url":null,"abstract":"22FDX™ is the industry's first FDSOI technology architected to meet the requirements of emerging mobile, Internet-of-Things (IoT), and RF applications. This platform achieves the power and performance efficiency of a 16/14nm FinFET technology in a cost effective, planar device architecture that can be implemented with ∼30% fewer masks. Performance comes from a second generation FDSOI transistor, which produces nFET (pFET) drive currents of 910μΑ/μm (856μΑ/μm) at 0.8 V and 100nA/μm Ioff. For ultra-low power applications, it offers low-voltage operation down to 0.4V V<inf>min</inf> for 8T logic libraries, as well as 0.62V and 0.52V V<inf>min</inf> for high-density and high-current bitcells, ultra-low leakage devices approaching 1pA/μm I<inf>off</inf>, and body-biasing to actively trade-off power and performance. Superior RF/Analog characteristics to FinFET are achieved including high f<inf>T</inf>/f<inf>MAx</inf> of 375GHz/290GHz and 260GHz/250GHz for nFET and pFET, respectively. The high f<inf>MAx</inf> extends the capabilities to 5G and milli-meter wave (>24GHz) RF applications.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 173
High performance, flexible CMOS circuits and sensors toward wearable healthcare applications 面向可穿戴医疗保健应用的高性能、柔性CMOS电路和传感器
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838358
K. Takei
{"title":"High performance, flexible CMOS circuits and sensors toward wearable healthcare applications","authors":"K. Takei","doi":"10.1109/IEDM.2016.7838358","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838358","url":null,"abstract":"Macroscale, flexible, and/or stretchable electronics enable to collect a variety of information by attaching it on diverse objects including nonplanar surfaces such as human body. To realize the devices, there are several technical challenges such as (1) low-cost, macroscale sensor network formation, (2) low power and high performance flexible circuits, and (3) other flexible components including battery and wireless communications. In this study, we propose and develop a low power flexible circuit platform using inorganic material-based complementary metal-oxide-semiconductor (CMOS) on a flexible substrate and printed macro-scale, multi-functional sensor networks to address the challenges.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122840570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond CMOS兼容MIM去耦电容器,具有可靠的亚纳米EOT高k堆栈,适用于7纳米及以上节点
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838382
T. Ando, E. Cartier, P. Jamison, A. Pyzyna, S. Kim, J. Bruley, K. Chung, H. Shobha, I. Estrada-Raygoza, H. Tang, S. Kanakasabapathy, T. Spooner, L. Clevenger, G. Bonilla, H. Jagannathan, V. Narayanan
{"title":"CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond","authors":"T. Ando, E. Cartier, P. Jamison, A. Pyzyna, S. Kim, J. Bruley, K. Chung, H. Shobha, I. Estrada-Raygoza, H. Tang, S. Kanakasabapathy, T. Spooner, L. Clevenger, G. Bonilla, H. Jagannathan, V. Narayanan","doi":"10.1109/IEDM.2016.7838382","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838382","url":null,"abstract":"We demonstrate a record-low EOT (equivalent oxide thickness) of 0.8 nm for a metal-insulator-metal (MIM) decoupling capacitor, which is compatible with back-end-of-line (BEOL) processing. This results in 2-plate MIM capacitance density of 43 fF/um2, and leakage current density (Jg) of 5 fA/um2 at 1V, 125 oC. Moreover, we identify that symmetry of CV/IV/TDDB characteristics for both positive and negative bias polarities is a key consideration for stacking more than one MIM capacitor for further capacitance density increase. We develop a novel tri-layer high-k stack with buffer layers between HfO2 and metal electrodes, which substantially improves the electrical bias symmetry, and achieve Vuse = 1.32 V (10 yr/1 ppm/1 cm2/125 oC) at EOT = 0.8 nm. These results should support record stacked-MIM (> 2-plate) capacitance densities, with sub-nm EOT, for the 7 nm node and beyond.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128741508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance 系统验证2nm直径垂直MTJ阵列和MgO势垒在10 nm以下的嵌入式STT-MRAM具有几乎无限的耐用性
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838493
J. Kan, C. Park, C. Ching, J. Ahn, L. Xue, R. Wang, A. Kontos, S. Liang, M. Bangar, H. Chen, S. Hassan, S. Kim, M. Pakala, S. H. Kang
{"title":"Systematic validation of 2x nm diameter perpendicular MTJ arrays and MgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance","authors":"J. Kan, C. Park, C. Ching, J. Ahn, L. Xue, R. Wang, A. Kontos, S. Liang, M. Bangar, H. Chen, S. Hassan, S. Kim, M. Pakala, S. H. Kang","doi":"10.1109/IEDM.2016.7838493","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838493","url":null,"abstract":"We present a comprehensive device and scalability validation of STT-MRAM for high performance applications in sub-10 nm CMOS by providing the first statistical account of barrier reliability in perpendicular magnetic tunnel junctions (pMTJs) from 70 to 25 nm diameter in 1 Gbit arrays. We have experimentally investigated the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, duty-cycle, and temperature. A large write-to-breakdown voltage window of > 1 V (> 20 σavg) was measured and a long time-to-breakdown was projected (> 1015 cycles) for 45 nm pMTJs, guaranteeing practically unlimited write cycles. We also reveal a dramatic enhancement of barrier reliability in conjunction with pMTJ size scaling down to 25 nm diameter, further widening the operating window at deeply scaled nodes.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Four-directional pixel-wise polarization CMOS image sensor using air-gap wire grid on 2.5-μm back-illuminated pixels 在2.5 μm背照像素上采用气隙线栅的四向像素偏振CMOS图像传感器
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838378
Tomohiro Yamazaki, Yasushi Maruyama, Yusuke Uesaka, Motoaki Nakamura, Y. Matoba, T. Terada, K. Komori, Y. Ohba, S. Arakawa, Yasutaka Hirasawa, Yuhi Kondo, J. Murayama, Kentaro Akiyama, Y. Oike, Shuzo Sato, T. Ezaki
{"title":"Four-directional pixel-wise polarization CMOS image sensor using air-gap wire grid on 2.5-μm back-illuminated pixels","authors":"Tomohiro Yamazaki, Yasushi Maruyama, Yusuke Uesaka, Motoaki Nakamura, Y. Matoba, T. Terada, K. Komori, Y. Ohba, S. Arakawa, Yasutaka Hirasawa, Yuhi Kondo, J. Murayama, Kentaro Akiyama, Y. Oike, Shuzo Sato, T. Ezaki","doi":"10.1109/IEDM.2016.7838378","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838378","url":null,"abstract":"Polarization information is useful in highly functional imaging. This paper presents a four-directional pixel-wise polarization CMOS image sensor using an air-gap wire grid on 2.5-μm back-illuminated pixels. The fabricated air-gap wire grid polarizer achieved a transmittance of 63.3 % and an extinction ratio of 85 at 550 nm, outperforming conventional polarization sensors. The pixel-wise polarizers fabricated with the wafer process on back-illuminated image sensors exhibit good oblique-incidence characteristics, even with small polarization pixels of 2.5 μm. The proposed image sensor realizes mega-pixel various fusion-imaging applications, such as surface reflection reduction, highly accurate depth mapping, and condition-robust surveillance.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Two-dimensional heterojunction interlayer tunnel FET (Thin-TFET): From theory to applications 二维异质结层间隧道FET (Thin-TFET):从理论到应用
2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI: 10.1109/IEDM.2016.7838451
Mingda Li, R. Yan, D. Jena, H. Xing
{"title":"Two-dimensional heterojunction interlayer tunnel FET (Thin-TFET): From theory to applications","authors":"Mingda Li, R. Yan, D. Jena, H. Xing","doi":"10.1109/IEDM.2016.7838451","DOIUrl":"https://doi.org/10.1109/IEDM.2016.7838451","url":null,"abstract":"We review the conception and development of two-dimensional heterojunction interlayer field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) and a high on-current are estimated theoretically. The Thin-TFET has been experimentally demonstrated using WSe2/SnSe2 stacked heterostructures, where the SS is mostly likely limited by the interfacial trap density of states and the parasitic MOSFET. Due to its vertical stacking structure, Thin-TFET intrinsically has a smaller gate-drain capacitance compared to the conventional lateral pin-TFET. In turn, this results in mitigated Miller Effect in Thin-TFET thus reducing dynamic energy dissipation in circuits.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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