CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond

We demonstrate a record-low EOT (equivalent oxide thickness) of 0.8 nm for a metal-insulator-metal (MIM) decoupling capacitor, which is compatible with back-end-of-line (BEOL) processing. This results in 2-plate MIM capacitance density of 43 fF/um2, and leakage current density (Jg) of 5 fA/um2 at 1V, 125 oC. Moreover, we identify that symmetry of CV/IV/TDDB characteristics for both positive and negative bias polarities is a key consideration for stacking more than one MIM capacitor for further capacitance density increase. We develop a novel tri-layer high-k stack with buffer layers between HfO2 and metal electrodes, which substantially improves the electrical bias symmetry, and achieve Vuse = 1.32 V (10 yr/1 ppm/1 cm2/125 oC) at EOT = 0.8 nm. These results should support record stacked-MIM (> 2-plate) capacitance densities, with sub-nm EOT, for the 7 nm node and beyond.