32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance

Abstract

A 32-bit commercial processor core is implemented at 5-nm design rules to study transistor and interconnect technology options and the impact of increasing interconnect resistance on system performance. Insights obtained are: 1) The major benefit of downscaling FET gate length is reducing MEOL parasitics instead of the intrinsic gate capacitance. 2) 2D-material-based FETs can achieve ∼2∗ better core-level energy-delay-product in theory compared to the projected Si FinFET; contact resistivity <6∗10−8 Ω-μm2 is required for 2D-FETs to match the core performance using Si FinFET. 3) Signal routing optimization can mitigate the impact of BEOL resistance such it contributes to 15%–35% of the total delay at the cost of using more cells and vias, which is not manifest if a ring oscillator with fixed wire load is used without performing full place-and-route. 4) Thinning Cu diffusion barrier can improve system performance up to 11% and alleviate BEOL variation impact.