Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.最新文献_第5页

Magnetic nanocomposites for organic compatible miniaturized antennas and inductors 磁性纳米复合材料用于有机兼容小型化天线和电感器

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432088

P. Markondeya Raj, P. Muthana, T. Xiao, L. Wan, D. Balaraman, I. R. Abothu, S. Bhattacharya, M. Swaminathan, R. Tummala

{"title":"Magnetic nanocomposites for organic compatible miniaturized antennas and inductors","authors":"P. Markondeya Raj, P. Muthana, T. Xiao, L. Wan, D. Balaraman, I. R. Abothu, S. Bhattacharya, M. Swaminathan, R. Tummala","doi":"10.1109/ISAPM.2005.1432088","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432088","url":null,"abstract":"Current wireless systems are limited by RF technologies in their size, communication range, efficiency and cost. RF circuits are difficult to miniaturize without compromising performance. Antennas and inductors are major impediments for system miniaturization because of the lack of magnetic materials with suitable high frequency properties. Keeping antenna and inductor requirements into consideration, two magnetic nanocomposite systems - silica coated cobalt-BCB and Ni ferrite-epoxy were investigated as candidate materials. Nanocomposite thick film structures (125-225 microns) were screen printed onto organic substrates. Parallel plate capacitors and single coil coplanar inductors were fabricated on these films to characterize the electrical and magnetic properties of these materials at low and high frequencies. Electrical characterization showed that the Co/SiO/sub 2/ nanocomposite sample has a permeability and a matching permittivity of /spl sim/10 at GHz frequency range making it a good antenna candidate. Both polymer matrix composites retain high permeability at 1-2 GHz.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129542372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Fundamentals of fluxless soldering technology 无焊剂焊接技术的基本原理

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432041

C.C. Lee, Jongsung Kim

{"title":"Fundamentals of fluxless soldering technology","authors":"C.C. Lee, Jongsung Kim","doi":"10.1109/ISAPM.2005.1432041","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432041","url":null,"abstract":"Fluxless (flux-free) soldering technology deals with investigating and developing techniques and methods that can eliminate the use of fluxes in the soldering process. The fluxless feature in soldering processes has become increasing more important and received more attention from industries because there are more and more devices and products that cannot take fluxes in the soldering process. Examples are MEMS devices, sensor devices, biomedical devices, and photonic devices. In addition, in flip-chip soldering processes with very small gap between chips and substrates, flux residues are hard to clean out or are embedded in the underfills. The residues may reduce the reliability of the resulting flip-chip devices. There are two basic fluxless approaches that have been reported. The first is to use chemicals or RF plasma to convert or to remove the oxide layer that already exists. The existence of oxide layer is the reason why the flux is needed in nearly all soldering operations. The second approach is to remove the root cause, which is solder oxidation. This is accomplished by producing the solder materials in a non-oxidizing environment, followed immediately by capping the solder with a barrier layer that would prevent oxygen from penetrating into the solder layer. In this paper, we first present the root cause of needing fluxes in the soldering process. The fluxless processes dealing with oxides are summarized. The four fundamental steps of the oxidation prevention approach are reported. A fluxless process based on Sn-rich Sn-Au alloys is described as an example to illustrate the fluxless fundamentals. Results show that strong and nearly void-free joints can indeed be produced using this new technology.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115494789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Electromigration in eutectic SnPb solder bumps with Ni/Cu UBM Ni/Cu UBM在共晶SnPb钎料凸起中的电迁移

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432047

S. Chiu, S. Liang, Chih Chen, S. Lin, C.M. Chou, Y.C. Liu, K.H. Chen

引用次数: 0

Process optimization of lead-free wafer-level underfill material used in chip scale packaging 芯片级封装中无铅晶圆级底填料的工艺优化

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432092

Y. Liu, G. Dutt, A. Xiao

{"title":"Process optimization of lead-free wafer-level underfill material used in chip scale packaging","authors":"Y. Liu, G. Dutt, A. Xiao","doi":"10.1109/ISAPM.2005.1432092","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432092","url":null,"abstract":"Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to perform underfill at the wafer-level, thereby eliminating multiple steps in the packaging process and cutting production cost significantly. However, lead-free solder poses significant challenge to this new technology. Compared to eutectic solder, lead-free solder tends to have a lower yield stress, requires higher reflow temperature and forms brittle joints. With increasing demand of lead-free compatible packaging material, further advancement of wafer level underfill material and process optimization are necessary to ensure compatibility with lead-free solders, better voiding performance and higher interconnection yield. We have developed novel wafer level underfill materials for chip scale packaging that are compatible with lead-free assembly. These materials, when coated on the wafer, form clear, transparent coating after B-stage that can be diced into coated dies without any delaminating and cracking. In this paper we discuss the effect of various heating profiles and different equipment used in the B-stage step on flow of underfill during the reflow, residual solvent after B-stage, solder paste smearing, and interconnection yield. By optimizing the material properties and B-stage conditions, we demonstrated that wafer level underfill material can achieve high interconnect yield without causing smearing and voiding in lead-free assembly.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125607518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fluxless Sn-rich Sn-Au flip-chip bonding using electroplating processes 电镀工艺无焊剂富锡锡金倒装片键合

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432070

Jongsung Kim, C.C. Lee

{"title":"Fluxless Sn-rich Sn-Au flip-chip bonding using electroplating processes","authors":"Jongsung Kim, C.C. Lee","doi":"10.1109/ISAPM.2005.1432070","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432070","url":null,"abstract":"In this study, we present a fluxless flip-chip bonding process based on the design of Sn-rich Sn-Au electroplated multilayer, i.e., Sn-rich composition range of 90-99 wt.%. The fluxless flip-chip bonding process has become increasingly more important and received more attention from industries because there are more and more devices and products that cannot tolerate the use of fluxes in the bonding processes. Examples are MEMS devices, sensor devices, biomedical devices, and photonic devices. Prior to this effort, we have successfully developed fluxless bonding processes using non-eutectic Sn rich Sn-Au structures deposited in high vacuum. Thermal evaporation in vacuum is relatively costly and hard to fabricate thick layers. Electroplating method appears to be an economical alternative. Other advantages of electroplating are low processing temperature and the ability to fabricate solder bumps of any geometry using the photolithographic process. Au and Sn are known to react easily to form Au-Sn compound even at room temperature. Thus we first investigate the electroplating mechanism of thin layer of Au over the thick layer of Sn to see if any interesting interaction happens. In this study, the fluxless characteristic is possible because the electroplated Sn layer is capped with a thin Au layer. It is interesting to find that the thin Au layer reacts with the underlying Sn to form AuSn/sub 4/ intermetallic layer, which is believed to prevent oxygen penetration into the Sn layer. The flip-chip bonding process is carried out in hydrogen environment to inhibit Sn oxidation. The electroplated Sn-Au solder bumps on silicon with 50/spl mu/m in height are flip chip bonded to borosilicate glass substrate, showing high joint quality. This new fluxless flip chip bonding process could play an important role in many applications where the use of flux is not allowed.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123962546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Lead free solder process development and reliability for handset application 手机应用的无铅焊料工艺开发和可靠性

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432056

S. Zhu, C. Nguyen

引用次数: 1

Dielectric loss control of high-k polymer composites by Coulomb blockade effects of metal nanoparticles for embedded capacitor applications 利用金属纳米颗粒的库仑阻断效应控制高k聚合物复合材料的介电损耗

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432082

Jiongxin Lu, K. Moon, Jianwen Xu, C. Wong

{"title":"Dielectric loss control of high-k polymer composites by Coulomb blockade effects of metal nanoparticles for embedded capacitor applications","authors":"Jiongxin Lu, K. Moon, Jianwen Xu, C. Wong","doi":"10.1109/ISAPM.2005.1432082","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432082","url":null,"abstract":"Novel materials for embedded passive applications are in great and urgent demands. High dielectric constant and low dielectric loss are the most important dielectric materials prerequisites for embedded capacitors. It was demonstrated by the authors' that the carbon black (CB)/epoxy composites achieved ultra high K (>13,000). High dielectric loss, however, is the key issue of this material system. In this presentation, a novel method was introduced to control the dielectric loss of dielectric composites by taking advantage of the Coulomb blockade effect, the well-known quantum effect of metal nanoparticles. The increased K value and decreased dissipation factor were observed by the incorporation of in-situ formed Ag nanoparticles. The remarkably increased dielectric constant of the interfacial polarization-based composites is due to the piling of charges at the extended interface. The reduced dielectric loss was observed in the high dielectric constant composite materials containing silver (Ag) nanoparticles in virtue of Coulomb blockade effect. Transmission electronic microscopy (TEM), scanning electron microscopy (SEM) and X-ray diffraction (XRD) were used to characterize the microstructure of the Ag/epoxy composites and the Ag/CB/epoxy composites in order to correlate the structure and morphology of the composites with the dielectric properties.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121635428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

The SnAgCu solder joint integrity in WLCSP for green conversion SnAgCu焊点完整性在WLCSP绿色转换

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432059

J. Lee, C. Chung, Chin-Chiang Liu, H. Tong

{"title":"The SnAgCu solder joint integrity in WLCSP for green conversion","authors":"J. Lee, C. Chung, Chin-Chiang Liu, H. Tong","doi":"10.1109/ISAPM.2005.1432059","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432059","url":null,"abstract":"WLCSP with Ni/Cu UBM and SnAgCu solder interconnect comply completely with European ROHS regulation. SnAgCu solder exhibits best solder joint thermal fatigue life in organic laminate BGA type package to organic PCB during gentle TCT condition, but whether means it can also work well in silicone die level package to organic PCB due to larger CTE mismatch during temperature cycling, is still necessary to be explored. In this report, the interfacial metallurgical reactions of solder joint of the combination of 0.3 mm SnAgCu solder ball and different melting point solder pastes such as Sn37Pb and Sn3.0Ag0.5Cu will be investigated in the wafer level CSP package with 0.5mm ball pitch. After appropriate SMT process at low, medium and high reflow temperature respectively on NSMD FR4 PCB with Cu-OSP surface finish, the sample is subject to TCT (-40-125/spl deg/C) 500 and 1000 cycle, then are followed by solder joint cross-section observation with SEM/EDX. The diverse failure mode on the metallurgical evolution in the interface and solder bulk itself is recorded to illustrate the solder joint integrity. The relationship among the fracture morphology and solder paste type is concluded as well. Furthermore, one new technology with polymer collar structure around the solder ball is integrated to discuss the whole SnAgCu solder joint integrity enhancement during the TCT test. A mature wafer level CSP with Sn37Pb solder ball will be used for comparison as well.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121343785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Impact of different flip-chip bump materials on bump temperature rise and package reliability 不同倒装芯片碰撞材料对碰撞温升和封装可靠性的影响

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432054

D. Chau, A. Gupta, C. Chiu, S. Prstic, S. Reynolds

{"title":"Impact of different flip-chip bump materials on bump temperature rise and package reliability","authors":"D. Chau, A. Gupta, C. Chiu, S. Prstic, S. Reynolds","doi":"10.1109/ISAPM.2005.1432054","DOIUrl":"https://doi.org/10.1109/ISAPM.2005.1432054","url":null,"abstract":"Recent trends in the semiconductor industry are driving a continuous increase in power dissipation, but require a lighter, more compact and thinner packaging technology. One of the concern areas is the increasing temperature of the C4 die bump. As the power continues to increase, the electrical current through the C4 die bump increases accordingly, resulting in increased bump temperature due to Joule self-heating and trace heating. The bump current density and temperature is now approaching levels where electromigration is a significant reliability concern. In order to fully understand and avoid this failure phenomenon, we need to know the C4 die bump temperature. However, the material property of the bump is also a major factor contributed to the bump temperature which must be evaluated. This paper discusses the methodology of measuring the C4 die bump temperature as well as results of our measurements. The experimental study includes variation of the bump current, the die power dissipation, different enabling thermal solutions and different bump materials. The experimental results show the effect of the Joule self-heating of the bump and the impact of the bump materials.","PeriodicalId":181674,"journal":{"name":"Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005.","volume":"84 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

An AlN-based high temperature package for SiC devices: materials and processing SiC器件用铝基高温封装:材料与加工

Proceedings. International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005. Pub Date : 2005-03-16 DOI: 10.1109/ISAPM.2005.1432068

Zhigang Lin, R. Yoon

引用次数: 19