Process optimization of lead-free wafer-level underfill material used in chip scale packaging

Abstract

Wafer-level underfilling is an emerging technology that consists of pre-applying the underfill material on wafer during the wafer fabrication process. The novel underfill material and the process enable the chip manufacturers to perform underfill at the wafer-level, thereby eliminating multiple steps in the packaging process and cutting production cost significantly. However, lead-free solder poses significant challenge to this new technology. Compared to eutectic solder, lead-free solder tends to have a lower yield stress, requires higher reflow temperature and forms brittle joints. With increasing demand of lead-free compatible packaging material, further advancement of wafer level underfill material and process optimization are necessary to ensure compatibility with lead-free solders, better voiding performance and higher interconnection yield. We have developed novel wafer level underfill materials for chip scale packaging that are compatible with lead-free assembly. These materials, when coated on the wafer, form clear, transparent coating after B-stage that can be diced into coated dies without any delaminating and cracking. In this paper we discuss the effect of various heating profiles and different equipment used in the B-stage step on flow of underfill during the reflow, residual solvent after B-stage, solder paste smearing, and interconnection yield. By optimizing the material properties and B-stage conditions, we demonstrated that wafer level underfill material can achieve high interconnect yield without causing smearing and voiding in lead-free assembly.