Packaging of Electronic and Photonic Devices最新文献

{"title":"Nonlinear Thermal and Mechanical Analysis in the Vibration of a Printed Wiring Board","authors":"Xiaoling He, R. Fulton","doi":"10.1115/imece2000-2243","DOIUrl":"https://doi.org/10.1115/imece2000-2243","url":null,"abstract":"\u0000 Nonlinear laminate theory is applied and extended for the printed wiring board dynamic analysis. Equations of motion for the isotropic laminates are derived for vibration response analysis of the simply supported printed wiring board under mechanical and thermal loads. Temperature variation in spatial domain is taken into consideration. The effect of the temperature variation on the response character is analyzed and demonstrated by means of numerical results. Modal analysis is made to predict the vibration behavior in terms of deflection and stresses. Lamina stresses are used for failure prediction.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126058065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Refrigeration Cooled Computers: Application and Review","authors":"R. Schmidt, M. Ellsworth, R. C. Chu, D. Agonafer","doi":"10.1115/imece2000-2274","DOIUrl":"https://doi.org/10.1115/imece2000-2274","url":null,"abstract":"\u0000 This paper outlines and discusses the application conditions pertinent to refrigeration cooling a computer processor at both the module and system level. Amongst the issues that are addressed are total refrigeration heat load (comprised of active and parasitic heat loads), coefficient of performance (COP), continuous operation (reliability, concurrent maintenance), system heat rejection, condensation formation, and temperature stability. The paper will then examine how a vapor compression refrigeration system has been incorporated in IBM’s high end (Gx) servers. Finally, the paper will touch upon some of the additional complexities of operation at very low temperatures (less than −40 °C).","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126979402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-Mechanical Analysis of an NCA Type of Chip-on-Glass Assemblies","authors":"Hsien-Chie Cheng, Ming-Hisao Lee, K. Chiang, Chung-Wen Chang","doi":"10.1115/imece2000-2245","DOIUrl":"https://doi.org/10.1115/imece2000-2245","url":null,"abstract":"\u0000 Since the electrical conduction in the COG assembly using a non-conductive adhesive takes place through the connection of the bump and the electrodes, the contact resistance can be applied to the evaluation of the design quality as well as the overall reliability of the particular assembly. It should be further noted that as reported in the literature (e.g., see Liu, 1996; Kristiansen et al, 1998; Nicewarner, 1999; Timsit, 1999), the contact resistance between the bump and the electrode on the substrate strongly depends on the contact stress and the contact area. A higher reliability of the packaging somewhat relies on better contact stability as well as larger bonding stresses.\u0000 In order to explore the physical contact behaviors of a non-conductive adhesive type of COG assemblies, the contact pressure during manufacturing process sequences and during the temperature variation are extensively investigated using a three-dimensional nonlinear finite element model. The so-called death-birth simulation technique is applied to model the manufacturing process sequences. The typical COG assemblies associated with two types of micro-bumps that are made of different materials: metal and composite are considered as the test vehicle. The contact stress between the electrode and the bump is extensively compared at each manufacturing sequence as well as at elevated temperature in order to investigate the corresponding mechanical interaction. Furthermore, the adhesion stresses of the adhesive are also evaluated to further investigate the possibilities of cracking or delamination within the adhesive and in its interfaces with the die and with the substrate. At last, a parametric finite element model is performed over number of geometry/material design parameters to investigate their impact on the contact/adhesion stresses so as to attain a better reliability design.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127578480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board","authors":"J. Lau, S. Pan, Chris Chang","doi":"10.1115/1.1400995","DOIUrl":"https://doi.org/10.1115/1.1400995","url":null,"abstract":"\u0000 In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications","authors":"J. Lau, S. Lee, S. Pan, Chris Chang","doi":"10.1115/1.1462626","DOIUrl":"https://doi.org/10.1115/1.1462626","url":null,"abstract":"\u0000 An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the micro VIP CSP PCB assembly is subjected to thermal cycling tests.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nonuniform Temperature Distribution in Electronic Devices Cooled by Flow in Parallel Microchannels","authors":"G. Hetsroni, A. Mosyak, Z. Segal","doi":"10.1109/6144.910797","DOIUrl":"https://doi.org/10.1109/6144.910797","url":null,"abstract":"\u0000 We fabricated a novel thermal microsystems (simulating a computer chip) consisting of a heater, microchannels, inlet and outlet plena and we studied the effect of the geometry on the flow and heat transfer. The vapor - water two-phase flow patterns were observed in the parallel microchannels through a microscope and high-speed video camera. It was observed that hydraulic instabilities occur. Existence of a periodic annular flow was also observed, which consist of a symmetrically distributed liquid ring surrounding the vapor core. Along the microchannel axis, the periodic dry zone appears and develops. The thermal visualization and temperature measurements of the heated device were carried out using infrared thermography. As long as the flow was single phase liquid, the forced convection heat transfer resulted in a moderate irregularity on the heated chip. These temperature differences do not cause damage to the device. The steady-state heat transfer for different types of microchannels has been studied also at the range of heat flux where phase change of the working fluid from liquid to vapor took place. Under conditions of flow boiling in microchannels, a significant enhancement of heat transfer was established. In the case of uniform heat flux the hydraulic instabilities lead to irregularity of temperature distribution on the heated chip. In the case of nonuniform heat flux the irregularity increased drastically.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Fatigue Analysis of PBGA Solder Joints With the Consideration of Damage Evolution","authors":"S. Lee, K. Newman, Livia Hu","doi":"10.1115/imece2000-2265","DOIUrl":"https://doi.org/10.1115/imece2000-2265","url":null,"abstract":"\u0000 This paper presents a computational thermal fatigue analysis for the life prediction of solder joints in a plastic ball grid array-printed circuit board (PBGA-PCB) assembly. The PBGA has a full grid array of 256 solder balls with 1.0 mm ball pitch. The PCB is a 4-layer FR-4 laminate with a thickness of 1.57 mm (62 mils). The assembly is subjected to −40∼125°C thermal cycling (one-hour cycle). Finite element analysis is performed to obtain the creep hysteresis loops. Based on a previously developed model, the evolution of damage is considered in the life prediction of solder joints. Besides, PCBs with various thicknesses (40 mils and 20 mils) are investigated. The results from different cases are compared and discussed.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134055837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Key Parameters Affecting Solder Joint Life of Chip Resistors and Chip Capacitors Mounted on Insulated Metal Substrate","authors":"N. Sangalli, D. Barker","doi":"10.1115/imece2000-2244","DOIUrl":"https://doi.org/10.1115/imece2000-2244","url":null,"abstract":"\u0000 Aluminum insulated metal substrate (IMS) is often used as an alternative to FR-4 to enhance heat dissipation in high power applications. Although IMS offers better heat dissipation, the solder joint life of leadless chip resistors and chip capacitors under thermal cycling can decrease. This is due to the higher mismatch of the coefficient of thermal expansion between the ceramic based components and the aluminum board.\u0000 This paper has two main objectives. One is to investigate the sensitivity of solder joint life of ceramic chip capacitor and chip resistor mounted on IMS to variations in dielectric thickness, board material, and solder thickness on. This sensitivity analysis is conducted with finite element analysis (FEA) simulation. The other objective is to determine the solder joint life for different resistor sizes at different temperature ranges with FEA modeling and experiment data. These results are presented in terms of design guidelines to be used in the selection of component size, board material, and temperature ranges, given an expected solder joint life.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133314461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Parametric Design and Reliability Analysis of WIT Wafer Level Packaging","authors":"Y. T. Lin, P. Tang, K. Chiang","doi":"10.1115/imece2000-2248","DOIUrl":"https://doi.org/10.1115/imece2000-2248","url":null,"abstract":"\u0000 The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress Concentration in a Connectorized Optical Fiber","authors":"J. Malluck, W. W. King","doi":"10.1115/imece2000-2242","DOIUrl":"https://doi.org/10.1115/imece2000-2242","url":null,"abstract":"\u0000 For the most part, analyses of fiber fractures in connectors have been in the form of postmortem fractography. Typically in these works, characteristics of prefracture stress states have been inferred from fracture surfaces, and plausible qualitative explanations have been advanced about the likely structural mechanics and circumstances leading to fractures. The authors and their colleagues have undertaken a number of investigations of relevant structural mechanics. These have served the useful purpose of elucidating gross mechanisms, but the influence of the fine details of stress distributions have been missing.\u0000 Considered here is a cylindrical-ferrule connector for which, typically, the ferrule is ceramic with an outside diameter of 2.5mm or 1.25mm. The fiber to be terminated is bonded into a small-bore axial hole (capillary) in the ferrule by an epoxy or similar adhesive. In addition, fiber insertion into the capillary is facilitated by ferrule designs that provide a conical entrance cavity leading to the capillary. A very high percentage of fiber failures, both in the laboratory and the field, occur at the transition region between the fiber and the capillary; so analysis is focused on that region.\u0000 The stress distribution within an optical fiber adhesively bonded to a ceramic ferrule is determined by the finite element method for uniform remote tension acting on the fiber. An axisymmetric model is constructed to represent the fiber, epoxy, and geometry of the ferrule under this particular loading condition. The resulting stress distribution is determined within the fiber and the epoxy layer using the ANSYS finite element code. Analysis of the stress distribution reveals the presence of two stress concentrations located at the surface of the fiber as the fiber enters the ferrule. One stress concentration occurs as the fiber encounters the epoxy within the conical cavity. The second stress concentration occurs as the fiber enters the capillary. These stress concentrations when combined with surface damage (flaws) may lead to fiber breakage. Further analysis reveals that a smooth fillet transition between entrance and capillary could significantly reduce the stress concentration at the capillary entrance. Finally, a simulation of epoxy debonding within the entrance cone reveals an increase of stress concentration at the capillary entrance.","PeriodicalId":179094,"journal":{"name":"Packaging of Electronic and Photonic Devices","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132042225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}