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2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)最新文献

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Simulation, Characterization and Parameter Extraction of Radiation Hardened MOSFET 辐射硬化MOSFET的仿真、表征及参数提取
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902358
Jay Hind Kumar Verma, Sudip Ghosh, Ashutosh Yadav, Y. Chauhan
{"title":"Simulation, Characterization and Parameter Extraction of Radiation Hardened MOSFET","authors":"Jay Hind Kumar Verma, Sudip Ghosh, Ashutosh Yadav, Y. Chauhan","doi":"10.1109/MOS-AK.2019.8902358","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902358","url":null,"abstract":"Radiation Hardened by design (RHBD) devices are used for space applications to immune from radiation effects. Here, aforementioned device characteristics of bulk RHBD device is investigated for width and length variation through device simulator. Results are compared and fitted using BSIM-BULK model through global scaling using IC-CAP. Device characteristics in terms of drain current, trans-conductance and drain conductance are evaluated at different device width and channel length. For fitting of the device characteristics, various parameters in the model are changed accordingly to cover the whole effect to form a global model card for all the mentioned devices in linear and saturation regions.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122443383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2 D analysis of self aligned LDMOS structures in terms of breakdown voltages 自对准LDMOS结构击穿电压的二维分析
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902446
S. Marjorie, P. Govindacharyulu, K. Kishore
{"title":"2 D analysis of self aligned LDMOS structures in terms of breakdown voltages","authors":"S. Marjorie, P. Govindacharyulu, K. Kishore","doi":"10.1109/MOS-AK.2019.8902446","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902446","url":null,"abstract":"This paper deals with breakdown voltage studies on a new Lateral diffusion MOSFFET(LDMOS), structure and dependence of the breakdown voltage, on state resistance etc., on the doping profile such as drift length under field oxide, diffusion time and the Lightly Doped Drain (LDD) dose. In this new structure the channel region (p body) and the LDD structure were formed by a self-aligned process. This approach leads to saving of one mask level during fabrication. On state resistance is also studied in these structures and an optimum drift length has been arrived at. It is shown that the breakdown voltage depends on the drift length only up to a certain value beyond which the breakdown voltage remains nearly constant. Breakdown voltages close to 100 V have been obtained in these structures. On state resistance is also studied in these structures and an optimum drift length has been arrived at. A 2D analysis was carried out on the various parameters such as the horizontal and vertical electric field patterns, the impact generation profiles, generation recombination, impact generation before and after breakdown, the carrier concentration, electron and hole current densities and the conduction current densities of the structure. The results are compared with a similar structure where there is no selfaligned structure.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128689916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of Low-Cost Silicon BiCMOS Technology for RF Applications 射频应用低成本硅BiCMOS技术的发展
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902466
S. Balanethiram, S. Pande, Ashutosh Kumar Singh, B. Umapathi, H. S. Jatana, N. Mohapatra, A. Chakravorty
{"title":"Development of Low-Cost Silicon BiCMOS Technology for RF Applications","authors":"S. Balanethiram, S. Pande, Ashutosh Kumar Singh, B. Umapathi, H. S. Jatana, N. Mohapatra, A. Chakravorty","doi":"10.1109/MOS-AK.2019.8902466","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902466","url":null,"abstract":"It is well known that combining the benefits of bipolar and CMOS (Complementary Metal Oxide Semiconductor) devices in BiCMOS technology, one can achieve better speed and power-density in microelectronic circuitry. In this work, we present the device design, process development and optimization of diffusion bipolar junction transistor (BJT), for the first time in India, for analog and RF applications. The baseline 180nm CMOS process of Semi-Conductor Lab (SCL) at Chandigarh is used to develop the BiCMOS process. All the TCAD simulations are calibrated with the measured data of baseline BJT from 180nm CMOS process with two different process splits. Calibrated simulations of our proposed silicon BJT show current gain > 90 and current driving capacity > 10 mA. The breakdown voltage of the transistor is above 25 V (BVCB0) with cut-off frequency (fT) and maximum oscillation frequency (fmax) more than 5 GHz and 3 GHz, respectively.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115937268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Simple Flip-Around Switch with Reduced Charge Injection for High Precision Single-Ended Switched-Capacitor Circuits 一种用于高精度单端开关电容电路的简单翻转开关，减少了电荷注入
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902421
Ravikumar Adusumalli, Rahul Thottathil, Krishna Kanth Gowri Avalur
{"title":"A Simple Flip-Around Switch with Reduced Charge Injection for High Precision Single-Ended Switched-Capacitor Circuits","authors":"Ravikumar Adusumalli, Rahul Thottathil, Krishna Kanth Gowri Avalur","doi":"10.1109/MOS-AK.2019.8902421","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902421","url":null,"abstract":"This paper presents a architecture to reduce charge injection in single-ended switched capacitor networks where high precision is inevitable. The key advantage of this architecture in switched capacitor network is that without any additional circuitry, the switch non-idealities like charge injection and clock feedthrough can be improved significantly. The design is done in 0.18µm TSMC process. The results shows that the proposed switching scheme is 50% more accurate compared to all other conventional techniques in handling charge injection modeling inaccuracies in CMOS switches.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125318392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOS-AK India 2019 Front Matter MOS-AK印度2019前沿问题
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/mos-ak.2019.8902377
{"title":"MOS-AK India 2019 Front Matter","authors":"","doi":"10.1109/mos-ak.2019.8902377","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902377","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131617791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GAA 3D Si-MOSFET Based Hybrid Biosensor with Integrated Amplifier 基于集成放大器的GAA 3D Si-MOSFET混合生物传感器
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902423
Nawaz Shafi, Jaydeep Singh Parmaar, Chitrakant Sahu, C. Periasamy
{"title":"GAA 3D Si-MOSFET Based Hybrid Biosensor with Integrated Amplifier","authors":"Nawaz Shafi, Jaydeep Singh Parmaar, Chitrakant Sahu, C. Periasamy","doi":"10.1109/MOS-AK.2019.8902423","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902423","url":null,"abstract":"In this paper, we have demonstrated an idea of integration of biosensing, amplifying, and noise suppression on a single chip through a hybrid configured biosensor. The proposed biosensor is based on embedded cavity gate all around (GAA) inversion mode conventional MOS device. Lookup table based Verilog-A models for p/n type devices for different biomolecules have been developed using Atlas device simulator. The biosamples have been calibrated by incorporating them as dielectric materials with specific dielectric permitivities in the nanogap cavity. Circuit level simulations have been carried in Cadence Virtuoso. The sensitivity performance of hybrid biosensor has been evaluated interms of shift in logic threshold voltage (ΔVLt/ΔK) and voltage gain (AV ). Further we have also investigated various hybrid biosensor configurations comprising of resistive load sensing stages. For APTES (K = 3.57), in CMOS configured hybrid topology AV and ΔVLt of ≈ 30 and ≈ 240mV respectively, whereas for resistive load topology are fond to be ≈ 17.5 and ≈ 200mV respectively.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116599534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET 新型铁电-介电负电容隧道场效应管的演示
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902381
N. Bagga, Nitanshu Chauhan, A. Bulusu, S. Dasgupta
{"title":"Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET","authors":"N. Bagga, Nitanshu Chauhan, A. Bulusu, S. Dasgupta","doi":"10.1109/MOS-AK.2019.8902381","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902381","url":null,"abstract":"In this paper, we propose a novel double gate Ferroelectric-Dielectric Negative Capacitance Tunnel FET (FDNC-TFET). A layer of ferroelectric material is kept near the source-channel junction to incorporate the impact of negative capacitance which arises due to the polarization of ferroelectric material. This amplifies the electric field and in turn enhances the tunneling probability. A well calibrated Sentaraus TCAD setup is used to simulate the proposed structure and the validity is proved by fitting the polarization-field curve with experimental data. We have compared the results of FDNC-TFET with Reference Tunnel FET (R-TFET) and found ~16× of improvement in the ON current. To justify the choice of ferroelectric-dielectric combination in the proposed structure, we have also compared the results of FDNC-TFET with the Full Ferroelectric Negative Capacitance Tunnel FET (FFNC-TFET), having a complete ferroelectric layer over the channel. The reported reduction in ambipolar current of our proposed work is ~25 times as compared to FFNC-TFET.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126549202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and Compact Modeling of Drain-Extended FinFET 漏极扩展FinFET的分析与紧凑建模
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902458
Vikash Kumar, Chetan Kumar Dabhi, Shivendra Singh Parihar, Y. Chauhan
{"title":"Analysis and Compact Modeling of Drain-Extended FinFET","authors":"Vikash Kumar, Chetan Kumar Dabhi, Shivendra Singh Parihar, Y. Chauhan","doi":"10.1109/MOS-AK.2019.8902458","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902458","url":null,"abstract":"In this article, a comprehensive simulation and the compact model of drain extended FinFET for high power application is presented. Power FinFETs with different drain-extension designs (i.e. (i) multi-fin drain extended FinFET (ii) planar drain-extended FinFET) are simulated and analysed using 3-D Technology Computer-Aided Design (TCAD) simulation. TCAD calibrated intrinsic FinFET is modeled by the industry standard BSIM-CMG model. To model the effect of quasi-saturation due to drain-extension, current dependent resistance model is used along with BSIM-CMG model. The model is validated with TCAD simulations and, can be used for high power circuit simulations.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123307451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
MOS-AK India 2019 Copyright Page MOS-AK印度2019版权页面
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/mos-ak.2019.8902388
{"title":"MOS-AK India 2019 Copyright Page","authors":"","doi":"10.1109/mos-ak.2019.8902388","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902388","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123024167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes 低技术节点绝热逻辑电路泄漏电流的影响
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902360
Tridib Sarma, C. Parikh
{"title":"Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes","authors":"Tridib Sarma, C. Parikh","doi":"10.1109/MOS-AK.2019.8902360","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902360","url":null,"abstract":"This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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