Praveen Pal, Yogesh Pratap, Mridula Gupta, S. Kabra
{"title":"Comparative analysis of oxides to improve performance of DC-MOS-HEMTs","authors":"Praveen Pal, Yogesh Pratap, Mridula Gupta, S. Kabra","doi":"10.1109/MOS-AK.2019.8902420","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902420","url":null,"abstract":"AlGaN/GaN High Electron Mobility Transistors (HEMTs) are considered as good candidate for high power and high speed applications. In this paper, a simulation study has been done to investigate the effect of different gate oxides on double channel DC-MOS-HEMTs (Double Channel Metal Oxide Semiconductor HEMTs). The impact of oxide thickness on performance of DC-MOS-HEMT has also been performed. The impact of change in oxide thickness has been analyzed for cut off frequency, maximum frequency, current gain, power gain and transconductance. HfO2 shows good pinchoff, high current gain = 57.3 dB, high unilateral power gain = 65.8 dB and highest transconductance of 757 mS/mm.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131832992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MOS-AK India 2019 Author Index","authors":"","doi":"10.1109/mos-ak.2019.8902435","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902435","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116240404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reconfigurable Math Accelerator for ultra-low power sensing workloads on IoT edge devices","authors":"Saksham Soni, Dileep Kurian, A. V, A. Sreenath","doi":"10.1109/MOS-AK.2019.8902425","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902425","url":null,"abstract":"Fast evolving algorithms in domains like machine learning/AI demand some level of programmability to remain market relevant. Current approaches to programmability such as DSP cores and FPGAs are not energy efficient and hence not suitable for power constrained IoT edge devices. This paper looks at an alternative approach to programmability through a coarse grain reconfigurable accelerator built as a library of mathematical functions implemented on a chassis. This architecture is implemented on Intel 14nm CMOS technology and takes an area of 0.015mm2 consuming less than 100uJ on typical workloads. Sensor fusion algorithms like Kalman and Madgwick filters are mapped onto this IP as a case study to verify the solution. The results show 100x improvement in power and performance compared to software implementation of these algorithm on generic DSP cores.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"MOS-AK India 2019 Conference Program Schedule","authors":"","doi":"10.1109/mos-ak.2019.8902441","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902441","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128759396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A.Sai Kumar, S. Chatterjee, M. Suri, S. Sadana, Akash Sharma, Pratiksha, Ashutosh Kumar Singh, A. Chawla, D. Sehgal, H. S. Jatana, U. Ganguly
{"title":"Verilog-A SPICE Model of PECVD SiO2 OTP Memory Device","authors":"A.Sai Kumar, S. Chatterjee, M. Suri, S. Sadana, Akash Sharma, Pratiksha, Ashutosh Kumar Singh, A. Chawla, D. Sehgal, H. S. Jatana, U. Ganguly","doi":"10.1109/MOS-AK.2019.8902433","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902433","url":null,"abstract":"Many emerging electronic devices are being used for computation, storage as well as several other purposes to decrease the scaling requirement of MOSFET. The accurate behavior prediction of such hybrid systems (MOSFET + Emerging) is a challenging task before their co-integration in hardware. This paper presents a Verilog-A compact model for our PECVD SiO2 MIM type one time programmable (OTP) memory device. We show strong agreement between the simulated results and experimental electrical-characterization. The characterization of the devices presents the one time switching from its pristine high resistance state (HRS ∼ GΩ) to extreme low resistance state (LRS ∼ 10Ω). DC and transient simulations of one transistor one OTP (1T1O) illustrates the capability of the proposed model for hybrid circuit simulations for different applications.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126898556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}