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2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)最新文献

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Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes 低技术节点绝热逻辑电路泄漏电流的影响
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902360
Tridib Sarma, C. Parikh
{"title":"Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes","authors":"Tridib Sarma, C. Parikh","doi":"10.1109/MOS-AK.2019.8902360","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902360","url":null,"abstract":"This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOS-AK India 2019 Author Index MOS-AK India 2019作者索引
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/mos-ak.2019.8902435
{"title":"MOS-AK India 2019 Author Index","authors":"","doi":"10.1109/mos-ak.2019.8902435","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902435","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116240404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfigurable Math Accelerator for ultra-low power sensing workloads on IoT edge devices 可重构数学加速器，用于IoT边缘设备上的超低功耗传感工作负载
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902425
Saksham Soni, Dileep Kurian, A. V, A. Sreenath
{"title":"Reconfigurable Math Accelerator for ultra-low power sensing workloads on IoT edge devices","authors":"Saksham Soni, Dileep Kurian, A. V, A. Sreenath","doi":"10.1109/MOS-AK.2019.8902425","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902425","url":null,"abstract":"Fast evolving algorithms in domains like machine learning/AI demand some level of programmability to remain market relevant. Current approaches to programmability such as DSP cores and FPGAs are not energy efficient and hence not suitable for power constrained IoT edge devices. This paper looks at an alternative approach to programmability through a coarse grain reconfigurable accelerator built as a library of mathematical functions implemented on a chassis. This architecture is implemented on Intel 14nm CMOS technology and takes an area of 0.015mm2 consuming less than 100uJ on typical workloads. Sensor fusion algorithms like Kalman and Madgwick filters are mapped onto this IP as a case study to verify the solution. The results show 100x improvement in power and performance compared to software implementation of these algorithm on generic DSP cores.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOS-AK India 2019 Conference Program Schedule MOS-AK印度2019年会议日程安排
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/mos-ak.2019.8902441
{"title":"MOS-AK India 2019 Conference Program Schedule","authors":"","doi":"10.1109/mos-ak.2019.8902441","DOIUrl":"https://doi.org/10.1109/mos-ak.2019.8902441","url":null,"abstract":"","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128759396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Verilog-A SPICE Model of PECVD SiO2 OTP Memory Device Verilog-A PECVD SiO2 OTP内存器件SPICE模型
2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902433
A.Sai Kumar, S. Chatterjee, M. Suri, S. Sadana, Akash Sharma, Pratiksha, Ashutosh Kumar Singh, A. Chawla, D. Sehgal, H. S. Jatana, U. Ganguly
{"title":"Verilog-A SPICE Model of PECVD SiO2 OTP Memory Device","authors":"A.Sai Kumar, S. Chatterjee, M. Suri, S. Sadana, Akash Sharma, Pratiksha, Ashutosh Kumar Singh, A. Chawla, D. Sehgal, H. S. Jatana, U. Ganguly","doi":"10.1109/MOS-AK.2019.8902433","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902433","url":null,"abstract":"Many emerging electronic devices are being used for computation, storage as well as several other purposes to decrease the scaling requirement of MOSFET. The accurate behavior prediction of such hybrid systems (MOSFET + Emerging) is a challenging task before their co-integration in hardware. This paper presents a Verilog-A compact model for our PECVD SiO2 MIM type one time programmable (OTP) memory device. We show strong agreement between the simulated results and experimental electrical-characterization. The characterization of the devices presents the one time switching from its pristine high resistance state (HRS ∼ GΩ) to extreme low resistance state (LRS ∼ 10Ω). DC and transient simulations of one transistor one OTP (1T1O) illustrates the capability of the proposed model for hybrid circuit simulations for different applications.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126898556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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