Reconfigurable Math Accelerator for ultra-low power sensing workloads on IoT edge devices

Fast evolving algorithms in domains like machine learning/AI demand some level of programmability to remain market relevant. Current approaches to programmability such as DSP cores and FPGAs are not energy efficient and hence not suitable for power constrained IoT edge devices. This paper looks at an alternative approach to programmability through a coarse grain reconfigurable accelerator built as a library of mathematical functions implemented on a chassis. This architecture is implemented on Intel 14nm CMOS technology and takes an area of 0.015mm2 consuming less than 100uJ on typical workloads. Sensor fusion algorithms like Kalman and Madgwick filters are mapped onto this IP as a case study to verify the solution. The results show 100x improvement in power and performance compared to software implementation of these algorithm on generic DSP cores.