2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)最新文献

Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors 过通电感对大栅极外围多指射频晶体管稳定性的影响

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902354

S. A. Ahsan, A. Pampori, Sudip Ghosh, S. Khandelwal, Y. Chauhan

{"title":"Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors","authors":"S. A. Ahsan, A. Pampori, Sudip Ghosh, S. Khandelwal, Y. Chauhan","doi":"10.1109/MOS-AK.2019.8902354","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902354","url":null,"abstract":"In this paper, the impact of source via-inductance on stability performance of large gate-periphery RF transistors is investigated in terms of Rollett’s stability factor (K-factor) using a small-signal equivalent circuit model. The RF device-under-test studied in this work is a commercial multi-finger GaN HEMT with a considerably large gate-periphery of 10 × 90 µm. A systematic analysis of the K-factor is done by deriving its mathematical expression in terms of the equivalent circuit intrinsic and extrinsic components. While gate-to-drain capacitance is unanimously considered to be the most critical component in determining the device stability performance, due to the formation of the feedback loop, the simulation and experimental results obtained in this work reveal potential regions of device instability in the form of peaks and valleys, that emerge as a manifestation of the coupling between the via-inductance and the intrinsic drain-to-source capacitance. This study is of significance particularly to multi-finger large gate-periphery devices since they have a reduced gate-resistance and therefore are driven further into instability. This work is expected to serve as a guideline in obtaining optimized multi-finger RF transistors with regard to stability.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129245514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering 基于SiGe应变工程的栅极全能硅纳米线晶体管性能评价

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902440

S. Dey, J. Jena, Tara Prasanna Dash, E. Mohapatra, S. Das, C. K. Maiti

引用次数: 0

Theoretical Modeling and Numerical Simulation of Elliptical Capacitive Pressure Microsensor 椭圆电容式微压力传感器的理论建模与数值仿真

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902333

R. B. Mishra, Seshadri Reddy Nagireddy, S. Bhattacharjee, A. Hussain

{"title":"Theoretical Modeling and Numerical Simulation of Elliptical Capacitive Pressure Microsensor","authors":"R. B. Mishra, Seshadri Reddy Nagireddy, S. Bhattacharjee, A. Hussain","doi":"10.1109/MOS-AK.2019.8902333","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902333","url":null,"abstract":"A capacitive pressure sensor consists of a movable diaphragm which causes change in capacitance for an applied pressure. In order to achieve high sensitivity, a thin diaphragm of large area is employed with a small separation gap. This introduces non-linearity, decreases the dynamic range and increases the size of the sensor. Thus, an optimum sensor design is necessary to balance these trade-offs. This paper presents theoretical modeling and numerical simulations on various performance parameters like diaphragm deflection, change in capacitance, mechanical and capacitive sensitivities and nonlinearity of a clamped and normal mode elliptical capacitive pressure sensor for 0 – 8 kPa operating pressure range. This analysis can form the basis for compact modelling (CM) of circular and elliptical capacitive pressure sensors for simulation with large scale circuits. In all the designs of elliptical and circular shape, the diaphragm thickness and separation gap are held constant at 7 µm and 1 µm respectively. The semi-major and semi-minor axes of the elliptical sensor have been varied from 100µm to 300 µm. We have taken into account the small deflection theory, Kirchhoff’s plate theory and pull–in phenomena while designing the model. To follow small deflection theory, the maximum diaphragm deflection is kept less than 1/10th of diaphragm thickness, and the maximum deflection is kept less than 1/4th of the separation gap to avoid pull-in.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125762964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Energy Efficient Binary Adders for Error Resilient Applications 用于纠错应用的高能效二进制加法器

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902400

S. Deepsita, Noor Mahammad Sk

{"title":"Energy Efficient Binary Adders for Error Resilient Applications","authors":"S. Deepsita, Noor Mahammad Sk","doi":"10.1109/MOS-AK.2019.8902400","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902400","url":null,"abstract":"Next Generation portable systems need to be geared up to address the challenges of energy efficient processing. Approximate Computing is one of the promising methodologies that relies on captivating property of inherent error resilience of various multimedia applications. This paper proposes quality - energy optimal approximate adders based on systematic decomposition of full adder and higher dimensional adders are designed using the energy efficient and low error full adders. Novel approximate full adder with 87.5% accuracy is designed. The 8-bit, 16-bit binary adders are analyzed by incorporating the designed full adder. The proposed 8-bit approximate adders have the accuracy of 75.2%, 56.6% for 3 bits, 4 bits approximation respectively. 16-bit approximate adder with 8-bit approximation have an accuracy of 43% for an energy savings of nearly 50%. The designed adders when employed in Image Blending, Average PSNR, PSNR-HVS, PSNR-HVSM are found to be around 78dB, 37dB, 41dB respectively. The Application of Image brightness enhancement is analyzed with different constants (50,100,128) and different image sizes. The Image denoising is implemented and the Average MSE is found to be 0.06 and 0.2 for Gaussian, Salt & Pepper Noised image of size 1024 × 1024. The proposed energy efficient adders can sufficiently be used in multimedia applications without much loss of PSNR in real time.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114249100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Optimization of electrical characteristics of Tunnel FET incorporating Gate Engineering 结合栅极工程的隧道场效应管电学特性优化

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902361

Susmitha Kothapalli, Ullas Pandey, B. Bhowmick

引用次数: 0

Study of CNTFET Based Pattern Recognition Circuits in Comparison With CMOS Technology 基于CNTFET的模式识别电路与CMOS技术的比较研究

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902429

S. Archana, B. Madhavi, I. V. Murlikrishna

引用次数: 0

Charge and Capacitance Compact Model for III-V Quadruple-Gate FETs With Square Geometry 方形几何III-V型四栅极场效应管的电荷和电容紧凑模型

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902393

Mohit D. Ganeriwala, E. G. Marín, F. Ruiz, N. Mohapatra

引用次数: 0

MOS-AK India 2019 Cover Page MOS-AK India 2019封面

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/mos-ak.2019.8902306

引用次数: 0

Strain Engineering in AlGaN/GaN HEMTs for Performance Enhancement 用于性能增强的AlGaN/GaN hemt应变工程

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902465

E. Mohapatra, S. Das, Tara Prasanna Dash, S. Dey, J. Jena, C. K. Maiti

引用次数: 0

Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design 更快验证片上系统到数字转换器的建模技术

2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) Pub Date : 2019-02-01 DOI: 10.1109/MOS-AK.2019.8902447

C. Chithra, N. Krishnapura

{"title":"Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design","authors":"C. Chithra, N. Krishnapura","doi":"10.1109/MOS-AK.2019.8902447","DOIUrl":"https://doi.org/10.1109/MOS-AK.2019.8902447","url":null,"abstract":"In this paper, we present the modeling techniques used for faster simulation and verification of a time to digital converter (TDC) IC, designed for India-based Neutrino Observatory. The mixed signal implementation of the TDC necessitates rigorous verification of the interaction between the digital and analog blocks. The paper discusses how the major analog circuits were reduced to logic level models in Verilog while retaining the required accuracy for faster top-level simulations. In order to facilitate quicker verification of the simulation results, a behavioral-level TDC model which has minimal common algorithm with the implemented system is developed. This model is used within self-checking testbenches to create a reference against which simulation results are validated. These modeling techniques enabled the automation of the verification process, thereby reducing the design verification time significantly. The simulation and verification of 600 test cases were completed in less than 9 hours, whereas the mixed signal simulation for a single test case would have taken several days to complete.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128036995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0