S. A. Ahsan, A. Pampori, Sudip Ghosh, S. Khandelwal, Y. Chauhan
{"title":"过通电感对大栅极外围多指射频晶体管稳定性的影响","authors":"S. A. Ahsan, A. Pampori, Sudip Ghosh, S. Khandelwal, Y. Chauhan","doi":"10.1109/MOS-AK.2019.8902354","DOIUrl":null,"url":null,"abstract":"In this paper, the impact of source via-inductance on stability performance of large gate-periphery RF transistors is investigated in terms of Rollett’s stability factor (K-factor) using a small-signal equivalent circuit model. The RF device-under-test studied in this work is a commercial multi-finger GaN HEMT with a considerably large gate-periphery of 10 × 90 µm. A systematic analysis of the K-factor is done by deriving its mathematical expression in terms of the equivalent circuit intrinsic and extrinsic components. While gate-to-drain capacitance is unanimously considered to be the most critical component in determining the device stability performance, due to the formation of the feedback loop, the simulation and experimental results obtained in this work reveal potential regions of device instability in the form of peaks and valleys, that emerge as a manifestation of the coupling between the via-inductance and the intrinsic drain-to-source capacitance. This study is of significance particularly to multi-finger large gate-periphery devices since they have a reduced gate-resistance and therefore are driven further into instability. This work is expected to serve as a guideline in obtaining optimized multi-finger RF transistors with regard to stability.","PeriodicalId":178751,"journal":{"name":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors\",\"authors\":\"S. A. Ahsan, A. Pampori, Sudip Ghosh, S. Khandelwal, Y. Chauhan\",\"doi\":\"10.1109/MOS-AK.2019.8902354\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the impact of source via-inductance on stability performance of large gate-periphery RF transistors is investigated in terms of Rollett’s stability factor (K-factor) using a small-signal equivalent circuit model. The RF device-under-test studied in this work is a commercial multi-finger GaN HEMT with a considerably large gate-periphery of 10 × 90 µm. A systematic analysis of the K-factor is done by deriving its mathematical expression in terms of the equivalent circuit intrinsic and extrinsic components. While gate-to-drain capacitance is unanimously considered to be the most critical component in determining the device stability performance, due to the formation of the feedback loop, the simulation and experimental results obtained in this work reveal potential regions of device instability in the form of peaks and valleys, that emerge as a manifestation of the coupling between the via-inductance and the intrinsic drain-to-source capacitance. This study is of significance particularly to multi-finger large gate-periphery devices since they have a reduced gate-resistance and therefore are driven further into instability. This work is expected to serve as a guideline in obtaining optimized multi-finger RF transistors with regard to stability.\",\"PeriodicalId\":178751,\"journal\":{\"name\":\"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MOS-AK.2019.8902354\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOS-AK.2019.8902354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors
In this paper, the impact of source via-inductance on stability performance of large gate-periphery RF transistors is investigated in terms of Rollett’s stability factor (K-factor) using a small-signal equivalent circuit model. The RF device-under-test studied in this work is a commercial multi-finger GaN HEMT with a considerably large gate-periphery of 10 × 90 µm. A systematic analysis of the K-factor is done by deriving its mathematical expression in terms of the equivalent circuit intrinsic and extrinsic components. While gate-to-drain capacitance is unanimously considered to be the most critical component in determining the device stability performance, due to the formation of the feedback loop, the simulation and experimental results obtained in this work reveal potential regions of device instability in the form of peaks and valleys, that emerge as a manifestation of the coupling between the via-inductance and the intrinsic drain-to-source capacitance. This study is of significance particularly to multi-finger large gate-periphery devices since they have a reduced gate-resistance and therefore are driven further into instability. This work is expected to serve as a guideline in obtaining optimized multi-finger RF transistors with regard to stability.