Development of Low-Cost Silicon BiCMOS Technology for RF Applications

Abstract

It is well known that combining the benefits of bipolar and CMOS (Complementary Metal Oxide Semiconductor) devices in BiCMOS technology, one can achieve better speed and power-density in microelectronic circuitry. In this work, we present the device design, process development and optimization of diffusion bipolar junction transistor (BJT), for the first time in India, for analog and RF applications. The baseline 180nm CMOS process of Semi-Conductor Lab (SCL) at Chandigarh is used to develop the BiCMOS process. All the TCAD simulations are calibrated with the measured data of baseline BJT from 180nm CMOS process with two different process splits. Calibrated simulations of our proposed silicon BJT show current gain > 90 and current driving capacity > 10 mA. The breakdown voltage of the transistor is above 25 V (BVCB0) with cut-off frequency (fT) and maximum oscillation frequency (fmax) more than 5 GHz and 3 GHz, respectively.