Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium最新文献_第2页

Scheduling jobs with machine-dependent processing times 使用与机器相关的处理时间调度作业

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559680

Yi-Feng Hung, Jui-ling Yang

引用次数: 0

Yield learning model for integrated circuit package assembly 集成电路封装组装成品率学习模型

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559753

A. Sarwar, S. Balasubramaniam, D. Walker

引用次数: 1

FASE: a scheduling environment for semiconductor fabrication FASE:用于半导体制造的调度环境

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559679

J. Shiu, T.-K. Hwang, Yen-Wen Huang, C. Tsai, W. Su, Y. Cheng, Shi-Chung Chang, C. Chien

引用次数: 4

Statistical optimization of high frequency LDMOS devices via hyper-fractionated experimental designs 基于超分馏实验设计的高频LDMOS器件统计优化

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559788

R. Elias, G. Ma, L. Golonka

引用次数: 1

Escape routing from chip scale packages 逃避芯片级封装的路由

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559771

E. Winkler

{"title":"Escape routing from chip scale packages","authors":"E. Winkler","doi":"10.1109/IEMT.1996.559771","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559771","url":null,"abstract":"Electronic packaging has steadily been miniaturized to reduce component weight and volume for portable applications and to enhance system speed performance. Package sizes approach the chip size in the chip size package (CSP) while retaining discrete package advantages in handling and test. In the CSP approach the ball interconnect (C5 balls) between package and mother board may be placed at pitches as low as 0.5 mm. There are, however, limitations to the number of escape vias/traces which mother boards can handle. These limits are a function of the C5 pad size and pitch, via land size and pitch, trace pitch and the number of C5 pads. In addition, features such as blind and buried vias can enhance the under-package escape routability but for PWBs these features bring a significant board cost penalty. This paper addresses escape layer count for full array CSPs and also depopulated array CSPs where C5 pads are only in outer C5 rings. For a full C5 array, using high density (0.5 mm) C5 pitch and leading edge PWB technology for the mother board (projected for the year 2000), only one signal ring can escape per PWB layer. The inner, smaller rings in this calculation with /spl sim/30% power and ground are routed to common power and ground planes. In order to succeed in full array escape within the PWB, the costly add-ons of filled, blind vias are required. With emerging high density interconnect (HDI) where via pads are in the range of 0.2 mm or less and trace pitch is about 0.1 mm, escape routing is readily achieved.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123100429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Next generation coating technologies for low-cost electronics manufacturing 低成本电子制造的下一代涂层技术

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559790

S. Bagen, G. Gibson, C. Newquist, H. Sago

引用次数: 5

A thin and low thermal resistance aluminum nitride BGA package for high speed DSP devices 一种用于高速DSP器件的薄而低热阻氮化铝BGA封装

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559694

N. Iwase, T. Yasumoto, H. Asai, J. Monma, K. Yano, H. Hayashida

{"title":"A thin and low thermal resistance aluminum nitride BGA package for high speed DSP devices","authors":"N. Iwase, T. Yasumoto, H. Asai, J. Monma, K. Yano, H. Hayashida","doi":"10.1109/IEMT.1996.559694","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559694","url":null,"abstract":"Low thermal resistance and high TCT (temperature cycle test) reliability have been attained by thin AlN BGA package structure. High speed signal transmission for multimedia DSP (digital signal processor) has been analyzed by computer simulation. The package has 0.6 mm body thickness, which is 1/3 of ordinary ceramic packages. A low thermal resistance of 4.8 /spl deg/C/W has been attained without a heat sink and with no air cooling while mounted on a PWB having 4 conductive layers. Scattering parameters were measured up to 9 GHz and applied to 250 MHz clock signal simulation. No deterioration of signal waveforms was observed during the simulation. The effects of package thickness and package size have been discussed from the thermal resistance and TCT reliability point of view. Thicker and larger package size provided lower thermal resistance. The developed package thickness and size (35/spl times/35 mm) have been determined by taking into account the application field of mobile PCs (personal computers) and through simulation. The package thickness versus TCT reliability has been discussed, and then the TCT has been carried out under an assembled condition on a PWB, and MTTF of 1 k cycles has been derived.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124084711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Self-aligning flip-chip assembly using eutectic gold/tin solder in different atmospheres 在不同气氛下使用共晶金/锡焊料的自对准倒装芯片组装

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559677

C. Kallmayer, H. Oppermann, G. Eugelmann, E. Zakel, H. Reichl

{"title":"Self-aligning flip-chip assembly using eutectic gold/tin solder in different atmospheres","authors":"C. Kallmayer, H. Oppermann, G. Eugelmann, E. Zakel, H. Reichl","doi":"10.1109/IEMT.1996.559677","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559677","url":null,"abstract":"New applications in the field of optoelectronic packaging as well as environmental concerns lead to a growing interest in fluxless assembly processes. Eutectic gold/tin solder offers the possibility of fluxless flip chip soldering on various substrate materials and substrate metallizations. It has been shown that gold/tin solder is applicable for flip chip assembly by different techniques. Using the self-alignment mechanism of the solder, cost effective flip chip assembly with high accuracy can be realized, as the process requires only coarse positioning prior to the soldering. The scope of this paper is to investigate the self-alignment capability of gold/tin solder for fluxless soldering processes in different atmospheres. During the soldering, the atmosphere determines the thickness of the oxide layer which inhibits the wetting of the pads and therefore the self-alignment. In this study, the impact of inert and reducing atmospheres on the self-alignment capability is investigated. The experiments are performed in nitrogen, active atmosphere and hydrogen. Vernier patterns on chips and substrates allow the quantification of the positioning accuracy. Comparing the results, a conclusion about the optimum atmosphere for self-aligning flip chip assembly can be drawn. As an example, the application of the choice process is shown for optoelectronic devices.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"2 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133114582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication 量化半导体晶圆制造周期缩短的效益

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559705

K. Nemoto, E. Akçalı, R. Uzsoy

引用次数: 48

Eutectic solder flip chip technology for chip scale package 芯片级封装用共晶焊料倒装技术

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559794

C. Takubo, N. Hirano, K. Doi, H. Tazawa, E. Hosomi, Y. Hiruta

引用次数: 7