J. Shiu, T.-K. Hwang, Yen-Wen Huang, C. Tsai, W. Su, Y. Cheng, Shi-Chung Chang, C. Chien
{"title":"FASE: a scheduling environment for semiconductor fabrication","authors":"J. Shiu, T.-K. Hwang, Yen-Wen Huang, C. Tsai, W. Su, Y. Cheng, Shi-Chung Chang, C. Chien","doi":"10.1109/IEMT.1996.559679","DOIUrl":null,"url":null,"abstract":"FASE is a computer-aided scheduling environment developed for semiconductor fabrication. Its current version includes: (1) a mid-term and daily scheduler, (2) a machine variability analyzer, (3) a what-if analysis tool and (4) a friendly graphic user interface (GUI). The scheduler is extended from an optimization-based scheduler for a R&D pilot line to a mass production fab application. To identify capacity and cycle time bottlenecks, a variability analyzer is developed, which functions jointly with the scheduler. The what-if analysis tool combines GUI technique, the scheduler and the variability analyzer to answer what-if questions on capacity variation, desired output variation, etc. Test results using field data indicate that FASE provides an decision aid in addressing many issues encountered in scheduling semiconductor fabrication.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559679","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
FASE is a computer-aided scheduling environment developed for semiconductor fabrication. Its current version includes: (1) a mid-term and daily scheduler, (2) a machine variability analyzer, (3) a what-if analysis tool and (4) a friendly graphic user interface (GUI). The scheduler is extended from an optimization-based scheduler for a R&D pilot line to a mass production fab application. To identify capacity and cycle time bottlenecks, a variability analyzer is developed, which functions jointly with the scheduler. The what-if analysis tool combines GUI technique, the scheduler and the variability analyzer to answer what-if questions on capacity variation, desired output variation, etc. Test results using field data indicate that FASE provides an decision aid in addressing many issues encountered in scheduling semiconductor fabrication.