{"title":"Ba/sub x/Sr/sub 1-x/TiO/sub 3/ thin films made by Turbodisc/sup TM/ PE-MOCVD techniques","authors":"Tingkai Li, P. Zawadzki, R. Stall","doi":"10.1109/IEMT.1996.559730","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559730","url":null,"abstract":"TurboDisc/sup (TM)/ and Plasma Enhanced MOCVD techniques have been used to deposit Ba/sub x/Sr/sub 1-x/TiO/sub 3/ (BST) thin films. The precursors for making the BST thin films were derived from Ba(thd)2, Sr(thd)2 and titanium isopropoxide (TIP). The BST thin films were deposited onto Pt/Ti/Si0/sub 2//Si wafers, Si (100) wafers and single-crystal sapphire substrates to measure their phase formation, thickness uniformity and electrical properties. Typically, 200 nm thick Ba/sub 0.5/Sr/sub 0.5/TiO/sub 3/ thin films on Pt electrodes have a dielectric constant of approximately 600, and a leakage current of less than 2/spl times/10/sup -7/ A/cm/sup 2/ at 100 kV/cm and room temperature. These characteristics suggest that the TurboDisc/sup (TM)/, PE-MOCVD technique could be used in the creation of reliable, high density memory devices. In addition, the relationship between composition, microstructure and electrical properties of BST thin films was also investigated.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127439459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The influence of pad geometry on ceramic ball grid array solder joint reliability","authors":"S. Yee, H. Ladhar","doi":"10.1109/IEMT.1996.559742","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559742","url":null,"abstract":"The reliability of the solder joints on dog bone pads with hot air solder levelling (HASL) finish was found to be statistically different and less reliable than other combinations. The reliability of all other combinations was not significantly different. Both pad geometries and surface finishes evaluated in this study produced excellent, reliable solder joints. The selection of the pad geometry and surface finish will not have significant impact on CBGA solder joint reliability. Since the study was based on mechanical deflection system (MDS) test technology, the limitations for MDS will apply. Additional accelerated thermal cycling (ATC) tests to verify the conclusion will definitely be of value.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126605332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Aschenbrenner, A. Ostmann, G. Motulla, E. Zakel, H. Reichl
{"title":"Flip chip attachment using anisotropic conductive adhesives and electroless nickel bumps","authors":"R. Aschenbrenner, A. Ostmann, G. Motulla, E. Zakel, H. Reichl","doi":"10.1109/IEMT.1996.559678","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559678","url":null,"abstract":"Flip chip attachments provide the highest interconnection density possible, which makes this technology very attractive for use with liquid crystal display (LCD) packaging methods. This technology stimulated the development of new interconnection techniques, such as anisotropic adhesives. However, several factors have hindered the wide use of this technology. These factors include the availability and costs of bumped wafers. IZM and TU-Berlin have addressed both of these concerns by establishing a wafer-bumping facility which uses electroless nickel bumps. The combination of anisotropic adhesives and electroless nickel bumps has the potential for a low-cost chip on glass (COG) and chip on flex (COF) bonding technology. In this paper two types of anisotropic adhesives were studied with an emphasis on the properties of COG and COF interconnections. The electrical and mechanical performance of the adhesive bonds was studied by evaluating initial contact resistance and mechanical adhesion as a function of temperature and humidity.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Kalukin, V. Sankaran, B. Chartrand, D. Millard, R. Kraft, M. Embrechts
{"title":"An improved method for inspection of solder joints using X-ray laminography and X-ray microtomography","authors":"A. Kalukin, V. Sankaran, B. Chartrand, D. Millard, R. Kraft, M. Embrechts","doi":"10.1109/IEMT.1996.559785","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559785","url":null,"abstract":"This paper describes the application of several imaging technologies available at the Center for solder joint inspection. X-ray laminography was combined with artificial neural networks to classify solder joints. Components with ball grid array, gull-wing and J-lead joints were imaged and several neural network methods were used to identify different classes of defects particularly significant to each type of joint. A novel probabilistic neural network approach for 2-D image classification has been developed which performs as well as or better than a conventional backpropagation network. The smear caused by the laminographic process poses a great challenge to accurate reconstruction and subsequent evaluation of the object. An improved method of accurately reconstructing the solder joint shape from the laminographic images has been developed as part of this research. The method removes artifacts caused by out-of-plane contributions, noise, and smear due to rotation of the source around the object while forming each laminograph, and can be adapted to consider the finite size of the aperture and X-ray scattering. Preliminary application of the method has produced dramatic improvements in the visual quality and signal-to-noise ratio for laminographs of experimental objects. More importantly, the ability to accurately measure the dimensions of the objects being imaged has been made possible by this approach. The possible extension of this work by using more X-ray projections and mathematically intensive routines brings this research into the realm of microtomography, which can help achieve more precise reconstruction at a much smaller scale. A new method of microtomography has been developed that can exceed previous limits in image resolution.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Intelligent process diagnosis based on end-of-line electrical test data","authors":"R. Guo, C. Tsai, Jian-Huei Lee, Shi-Chung Chang","doi":"10.1109/IEMT.1996.559754","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559754","url":null,"abstract":"The goal of this research is to develop a fuzzy logic-based system for a first-cut end-of-line diagnosis function. Based on measured abnormal electrical test data, the system provides the engineers a list of prioritized causes (process steps) for further investigation. The intelligent diagnosis system consists of three major modules: fuzzy modeling, knowledge base and inference engine. Experienced engineers diagnosis knowledge is captured in the knowledge base using fuzzy logic knowledge representation models. Each major processing step's fault possibility is calculated in the inference engine. The intelligent diagnosis system has been validated against 23 real fab cases. Results show that version 2.0 of the system identifies the real causes as the top three causes in 20 cases. Our analysis indicates that the inference engine is robust but the knowledge base is insufficient. Improvement strategy has been to periodically update the knowledge base by field engineers based on lessons learned from the case study.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123165004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An overview of the Chinese electronics industry","authors":"K. Tilley, D.J. Williams","doi":"10.1109/IEMT.1996.559751","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559751","url":null,"abstract":"The Chinese electronics industry is being driven to improve by a combination of domestic reform and foreign investment. The current size of the industry and the most important regional concentrations are reviewed. Current process capabilities are shown to range from state-of-the-art to a lag of up to 12 years when compared to world levels. Some doubts are cast on whether manufacturing processes are well integrated into an efficient manufacturing system.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Warpage and mechanical strength studies of ultra thin 150 mm wafers","authors":"M. Grief, J. A. Steele","doi":"10.1109/IEMT.1996.559727","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559727","url":null,"abstract":"Demand for die produced on ultra thin silicon substrates requires improvement in wafer thinning capability, manufacturing equipment substrate handling and packing methodologies. Existing methods typically consider substrates that are nominally flat and relatively thick (254 /spl mu/m to 613 /spl mu/m). The challenge COM 1 faces on several of its product lines, is that they require that the 150 mm diameter substrate be thinned to below 150 /spl mu/m. Wafers at this thickness will tend to bow and warp with unpredictable orientation. This is due to the interaction between stresses from the various frontside and backside dielectric and conductive layers together with those induced by the backside grinding and chemical thinning and the reduced ability of the thin silicon substrate to resist these forces. Existing schemes used for smaller wafer diameters (<100 mm) have proven incapable of successfully thinning, handling and transferring these larger substrates to the assembly sites, resulting in high levels of wafer breakage. To enhance survivability during subsequent handling and shipment of ultra-thin 150 mm wafers, the understanding of warpage and die strength becomes critical, which is the focus of this paper.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High complexity PCB's for enhanced SMT and bare chip assembly applications","authors":"S. Ehrler, R. Mayer, W. Olbrich, M. Roesch","doi":"10.1109/IEMT.1996.559718","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559718","url":null,"abstract":"New build-up technologies are necessary to meet the demands of future PC-boards. In this paper the DYCOstrate and PERL technologies are presented which use plasma etching for hole generation. These technologies offer advantages such as higher routing density, layer count reduction and lower production cost. Process flows are explained and possible constructions and design rules are presented. Electrical performance and reliability investigations have also been considered.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic classification of wafer defects: status and industry needs","authors":"Arye Shapiro","doi":"10.1109/IEMT.1996.559702","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559702","url":null,"abstract":"This paper describes the Automatic Defect Classification (ADC) beta site evaluations performed as part of the SEMATECH ADC project. Two optical review microscopes equipped with ADC software were independently evaluated in manufacturing environments. Both microscopes were operated in bright-field mode with white light illumination. ADC performance was measured on three process levels of random logic devices: source/drain, polysilicon gate, and metal. ADC performance metrics included classification accuracy, repeatability, and speed. In particular, ADC software was tested using a protocol that included knowledge base tests, gauge studies, and small passive data collections.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132525205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Microsystems for medical applications","authors":"A. Val, D. Estève, C. Val","doi":"10.1109/IEMT.1996.559776","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559776","url":null,"abstract":"The different 3D interconnection techniques have been initially applied to memories for a couple of main reasons market and easiness. With the development of a 3D technique from 1988, first at THOMSON-CSF and after at 3D PLUS, other criteria have been taken in account: stacking of the heterogeneous components, civilian applications which could be ruggedized later, and very low cost compatible with communication, automotive and medical applications. To allow this, each of the six operations of the flow chart are derived from large scale manufacturing in connected domains: devices are mounted into foils, taken from the smart cards manufacturing \"Reel to Reel process\" developed by GEMPLUS, same plastic moulding than the encapsulation technique of dice into plastic packages, plating identical to the metallized holes process in the printed circuit board industry, and laser etching by the mean of a YAG marking laser.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}