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Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium最新文献

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Impact of wafer probe damage on flip chip yields and reliability 晶圆探头损坏对倒装晶片良率及可靠性的影响
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559745
M.J. Varnau
{"title":"Impact of wafer probe damage on flip chip yields and reliability","authors":"M.J. Varnau","doi":"10.1109/IEMT.1996.559745","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559745","url":null,"abstract":"(Author's note: A large number of the samples built for this experiment were destroyed in an equipment malfunction. The samples were re-manufactured for the entire experiment. This resulted in long term test results not being available at press time. Additional results will be presented at the IEMT Symposium.) Reliability concerns have historically precluded electrical probing of wafers before the flip chip bumping process. The described experiments show that the bumping process as practiced by Delco Electronics and its commercial bumping venture Flip Chip Technologies has an Under-Bump-Metallurgy (UBM) that is able to tolerate wafer probing before bumping. The quality and bump reliability of a probed wafer is no different than a bump that did not see wafer probe before the bumping process.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"70 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132761308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Evaluating the environment, safety and health impacts of semiconductor manufacturing at the design and process development stages 在设计和工艺开发阶段评估半导体制造对环境、安全和健康的影响
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559736
W. Lashbrook, P. O'Hara
{"title":"Evaluating the environment, safety and health impacts of semiconductor manufacturing at the design and process development stages","authors":"W. Lashbrook, P. O'Hara","doi":"10.1109/IEMT.1996.559736","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559736","url":null,"abstract":"Design for the Environment Health and Safety (DFESH) is the integration of ESH principles into the Semiconductor product's life cycle. The DFESH program fulfills the key semiconductor industry ESH roadmap strategic issues of ESH design tools and ESH integration into the manufacturing process. This SEMATECH project is designed to delineate the strategy for this integration. The project consists of four elements: (1) Developing a semiconductor industry DFESH strategy (or an industry bluebook on DFESH). The product of this element is the roadmap for DFESH in the semiconductor industry. (2) Determining a set of semiconductor industry DFESH metrics and assessing the current state of the semiconductor industry. This element allows the project's customer to measure their progress in implementing DFESH. (3) Developing a set of DFESH tools to assist management and engineering in integration of DFESH into new process/materials selection. The three DFESH tools currently under development are: (A) A risk assessment tool which assists process engineering in chemical and process selection. (B) process materials/energy balance tool for semiconductor equipment and factory modeling. This tool is to assist in chemical and process selection as well as assessing material and energy use. (C) An Environmental Safety and Health (ESH) Cost of Ownership model which determines the cost and return of implementing ESH requirements. (4) Creation of a DFESH training and communications program which educates member companies and supplier staffs on philosophy. This paper will provide an overview of the SEMATECH DFESH program, and highlight the chemical risk assessment model's progress to date.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116586927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Prototype sensor and data acquisition system for the CILAP polymer deposition process 用于CILAP聚合物沉积过程的原型传感器和数据采集系统
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559786
A. Krauss, T. Miller
{"title":"Prototype sensor and data acquisition system for the CILAP polymer deposition process","authors":"A. Krauss, T. Miller","doi":"10.1109/IEMT.1996.559786","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559786","url":null,"abstract":"Improved process control is important in reducing the cost of microelectronics fabrication and electronics packaging. The goal of this paper is to present the findings from the design and implementation of a sensor and data acquisition system for an extrusion polymer deposition tool. The developed system will provide a platform for intelligent process control that will automate microelectronics fabrication machines, making them more suitable for assembly line or fabrication lab use. Covered are the construction of the sensor system at Dow and results from coating runs performed while the sensor system was collecting data. Examination of the data revealed several important relationships between the values sensed in real-time and post-process performance measurements. Film thickness is shown to relate to system pressures. Also, temperature effects and physical restraints on the extruder die are shown to significantly affect polymer flow, suggesting a means of actuation for intelligent process control.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125963661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 'virtual waferscale' multichip module system 一个“虚拟晶圆级”多芯片模块系统
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559712
R. Artus
{"title":"A 'virtual waferscale' multichip module system","authors":"R. Artus","doi":"10.1109/IEMT.1996.559712","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559712","url":null,"abstract":"A new concept in multichip modules is presented that represents a potential 'next step' in packaging for solid state electronic systems. A unique heat sink material, in the form of a compacted particulate paste provides a firm three dimensional support to die without adhesion to the die. The material also provides a direct thermal shunt between a die and its casing. The resulting low thermal resistance /spl Theta//sub jc/ allows an array of die to be placed into a single module where the die spacing can be such that direct die to die interconnects are possible. A dense array of die with direct die to die interconnects will behave electronically as if it were a single die. A 'virtual waferscale' 128 Mb SRAM memory block, fabricated as a 32 die array, is considered.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129069683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Activity based enterprise analysis through modeling 通过建模进行基于活动的企业分析
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559704
A. Vadgama, W. Trybula
{"title":"Activity based enterprise analysis through modeling","authors":"A. Vadgama, W. Trybula","doi":"10.1109/IEMT.1996.559704","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559704","url":null,"abstract":"While the applications of various modeling tools, i.e., Arena WFT, AutoSched, and Mansim, have provided an improved method of analyzing the performance of semiconductor-fabrication facilities, there is always more information that can be employed to improve performance. Activity Based Costing (ABC) has received significant attention as a means of identifying cost drivers that impact the facility output. Modeling is forward looking, while ABC has a historical perspective. Combining the modeling tools and the ABC activity provides a method of identifying the areas that will have the largest impact in the future. Once identified, corrective action can be taken.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"125 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120891853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High reliable FC-PBGA 高可靠性FC-PBGA
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559696
Y. Ishida, T. Katoh, S. Ishiwata, A. Omura, T. Oohara
{"title":"High reliable FC-PBGA","authors":"Y. Ishida, T. Katoh, S. Ishiwata, A. Omura, T. Oohara","doi":"10.1109/IEMT.1996.559696","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559696","url":null,"abstract":"This paper is concerned with the high reliability of FC-PBGA (Flip Chip-Plastic Ball Grid Array). While flip chip technology is experienced in watch assembly and has a cost advantage, the chip sizes for watches are too small and not directly applicable to high reliable FC-PBGA. Considering the application of FC technology to FC-PBGA, the bump structure change for lower stress will be effective. For this change, three steps have been under examination: (1) application of FC assembly to peripheral bump structure, (2) establishment of re-distribution structure on chip, and (3) application of FC technology to area array bump structure. The result of the first step, application of FC assembly to peripheral bumping is reported in this paper. The bump structure has ensured a thermal fatigue resistance 3,000 cycles under the condition -40 C 30 min/125 C 30 min.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131763592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reliability investigations of different bumping processes for flip chip and TAB applications 倒装芯片和标签应用中不同碰撞工艺的可靠性研究
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559743
E. Jung, J. Kloeser, J. Nave, G. Engelmann, L. Dietrich, E. Zakel, H. Reichl
{"title":"Reliability investigations of different bumping processes for flip chip and TAB applications","authors":"E. Jung, J. Kloeser, J. Nave, G. Engelmann, L. Dietrich, E. Zakel, H. Reichl","doi":"10.1109/IEMT.1996.559743","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559743","url":null,"abstract":"Presently, a number of bump metallurgies are used for flip chip and TAB technology. However, no conclusive characterisation of the processes used and reliability obtained is available up to now. For wafer bumping, alloys of electroplated PbSn5, PbSn63, AuSn20 and metals like Au are used as well as electroless Ni(P)-Au deposition. Flexible bumping processes like Au stud bumping and mechanical bumping with PbSn solders on a solder wettable UBM are evaluated as alternatives, which are of essential importance for flip chip or TAB especially for small and medium volume applications. Reliability investigations on these used metallurgies are performed. The mechanical stability of the bumps is tested after thermal cycling, taking special care in the determination of the failure mode. Finally, the results are characterized, compared and evaluated.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123751492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A projection for a 300 mm wafer fabricator in 2001 2001年300毫米晶圆制造商的投影
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559709
S. Balaji, J.A. Shapiro, K. Gardiner
{"title":"A projection for a 300 mm wafer fabricator in 2001","authors":"S. Balaji, J.A. Shapiro, K. Gardiner","doi":"10.1109/IEMT.1996.559709","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559709","url":null,"abstract":"This paper summarizes the work of nineteen students in a graduate class offered during the Winter/Spring semester of 1996 in an MS in Manufacturing Systems Engineering program. There is an assessment of the manufacturing technologies and tooling needed for the realization of an advanced microprocessor-like product in 2001. A representative 'typical' process routing was developed by examining leading-edge products and current projections. The fab will process 300 mm wafers and ship naked die. There are estimates of capital costs, and potential production volumes, these are somewhat scalable and afford a method for benchmarking and gauging future trends in this industry.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Equipment fault detection with fitted wafer surfaces 贴合硅片表面的设备故障检测
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559758
M. M. Gardner, J.C. Lu, R.S. Gyuresik, J. Wortman, B. Hornung, H. Heinisch, E. Rying
{"title":"Equipment fault detection with fitted wafer surfaces","authors":"M. M. Gardner, J.C. Lu, R.S. Gyuresik, J. Wortman, B. Hornung, H. Heinisch, E. Rying","doi":"10.1109/IEMT.1996.559758","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559758","url":null,"abstract":"This paper describes a new methodology for equipment fault detection. This methodology consists of fitting a thin-plate spline to post-process spatial data in order to construct a virtual wafer surface. The virtual wafer surface is then compared to an established baseline process surface, and the resulting spatial signature is used to detect equipment faults. Statistical distributional studies of signature metrics using a parametric bootstrapping technique provide the justification of determining the significance of the signature. Data collected from a Rapid Thermal Chemical Vapor Deposition (RTCVD) process is used to illustrate the procedures. This method detected equipment faults for all 11 wafers that were subjected to induced equipment faults.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126101334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Improved product delivery through employing a cost focus 通过采用成本焦点改进产品交付
Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559793
D. Murphy
{"title":"Improved product delivery through employing a cost focus","authors":"D. Murphy","doi":"10.1109/IEMT.1996.559793","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559793","url":null,"abstract":"Work schedules that successfully blend business, employee, and health and safety requirements are called \"best cost schedules\". A best cost schedule is not a day-off pattern or a shift length; it is the most cost-effective method to deploy equipment and personnel with employee buy-in and specific work/pay and coverage policies. Best cost schedules can save manufacturers millions of dollars every year.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127121580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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