{"title":"A 'virtual waferscale' multichip module system","authors":"R. Artus","doi":"10.1109/IEMT.1996.559712","DOIUrl":null,"url":null,"abstract":"A new concept in multichip modules is presented that represents a potential 'next step' in packaging for solid state electronic systems. A unique heat sink material, in the form of a compacted particulate paste provides a firm three dimensional support to die without adhesion to the die. The material also provides a direct thermal shunt between a die and its casing. The resulting low thermal resistance /spl Theta//sub jc/ allows an array of die to be placed into a single module where the die spacing can be such that direct die to die interconnects are possible. A dense array of die with direct die to die interconnects will behave electronically as if it were a single die. A 'virtual waferscale' 128 Mb SRAM memory block, fabricated as a 32 die array, is considered.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559712","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A new concept in multichip modules is presented that represents a potential 'next step' in packaging for solid state electronic systems. A unique heat sink material, in the form of a compacted particulate paste provides a firm three dimensional support to die without adhesion to the die. The material also provides a direct thermal shunt between a die and its casing. The resulting low thermal resistance /spl Theta//sub jc/ allows an array of die to be placed into a single module where the die spacing can be such that direct die to die interconnects are possible. A dense array of die with direct die to die interconnects will behave electronically as if it were a single die. A 'virtual waferscale' 128 Mb SRAM memory block, fabricated as a 32 die array, is considered.