Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium最新文献_第5页

A graph-based approach to disassembly model for end-of-life product recycling 基于图的报废产品回收拆解模型

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559739

H. Zhang, T. Kuo

{"title":"A graph-based approach to disassembly model for end-of-life product recycling","authors":"H. Zhang, T. Kuo","doi":"10.1109/IEMT.1996.559739","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559739","url":null,"abstract":"Manufacturing industries are beginning to face one of the consequences resulting from the rapid development which has occurred during the last decade. The most evident effect is that landfill capacity is being used up. Therefore, a systematic approach to recycling is both urgent and imperative. It has been also recognized that appropriate disassembly of used products is necessary in order to make recycling economically and environmentally viable in the current state of the art reprocessing technology. This paper proposes a graph-based heuristic approach to the disassembly model. The model is embedded on a graph representation and object-oriented modeling, which is obtained by generating disassembly sequences. Information exchange within the disassembly model is done through three phases: (1) disassembly analysis, (2) database and data management, and (3) recycling cost minimization. With graph representation, the problem of identifying the optimal disassembly and recycling strategy is transformed into a graph search problem. By solving the graph search problem, one can determine the termination of disassembly, generate the disassembly sequence, calculate the disassembly cost, select recycling plans, monitor the material flow, and evaluate environmental compatibility of the product. In addition, this paper illustrates the prototype using personal computer disassembly as an example.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

A method for the measurement of chip to leadframe adhesion in LOC packages 一种测量LOC封装中芯片与引线框架粘附性的方法

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559772

S. Ahmad, T. Jiang, W. Moden, C. Breen, J. Reeder

引用次数: 0

Statistical experimental design for MBE process characterization MBE工艺表征的统计实验设计

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559765

K. Lee, R. Bicknell-Tassius, G. Dagnall, A. Brown, G. May

{"title":"Statistical experimental design for MBE process characterization","authors":"K. Lee, R. Bicknell-Tassius, G. Dagnall, A. Brown, G. May","doi":"10.1109/IEMT.1996.559765","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559765","url":null,"abstract":"This paper presents a statistically designed experiment for systematic characterization of the molecular beam epitaxy (MBE) process to quantitatively describe the effects of process conditions on the qualities of grown films. This methodology is applied to a five-layer, undoped AlGaAs and InGaAs single quantum well structure grown on a GaAs substrate. Six input factors (time and temperature for oxide removal, substrate temperatures for AlGaAs and InGaAs layer growth, beam equivalent pressure of the As source and quantum well interrupt time) are examined by means of a Resolution IV, 2/sup 6-2/ fractional factorial design requiring sixteen trials. Several responses are characterized, including defect density, X-ray diffraction, and photoluminescence. Results indicate that the manipulation of each of the six factors over the ranges examined are statistically significant and lead to considerable variation in the responses. Following characterization, backpropagation neural networks are trained to model the process responses. The neural process models exhibit very good agreement with experimental results.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121095918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Restructuring manufacturing process flows 重组制造流程

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559748

N. Kane

{"title":"Restructuring manufacturing process flows","authors":"N. Kane","doi":"10.1109/IEMT.1996.559748","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559748","url":null,"abstract":"At Xilinx, Inc. a new manufacturing execution system, the Advanced Manufacturing System (AMS), is being jointly designed, developed and implemented with TIBCO, Inc. to replace a proprietary application. The system architecture is a radical departure from current market solutions. Two key features that differentiate this new tool are an automated flow determination model, for prescriptive processing, and modular flow designs incorporating a high degree of reusable modules. The system determination of lot routing removes a level of decision making from the system user and eliminates a source of error. The process flow model, analogous to the product design concept of postponement, incorporates the concept of early standardization and late customization. A hierarchically nested flow design allows for maximum reuse of standard \"code cells\" at the higher levels of the flow model and unique modules at lower levels. The conversion from the proprietary system to the new commercial application is a work-in process. System modeling began in the summer of 1995. The first release of production code was delivered in December, 1995. The conversion to the AMS application is occurring in stages throughout the spring and summer of 1996. This paper describes some of the technical challenges addressed by the product development team.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Yield of silicon selective epitaxial growth and its role in the production planning and control of three-dimensional semiconductor devices 硅选择性外延生长的产率及其在三维半导体器件生产计划和控制中的作用

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559732

S. Chen, C. Takoudis, R. Uzsoy

{"title":"Yield of silicon selective epitaxial growth and its role in the production planning and control of three-dimensional semiconductor devices","authors":"S. Chen, C. Takoudis, R. Uzsoy","doi":"10.1109/IEMT.1996.559732","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559732","url":null,"abstract":"We focus on the yield (Y) and growth rate (G) of silicon selective epitaxial growth (SEG) at 820 to 970/spl deg/C, and pressures between 40 and 150 Torr. Since the yield of silicon SEG is a potential bottleneck in the manufacture of three-dimensional integrated circuits, e.g., 3-D CMOS, basic knowledge of Y and its dependence on operating conditions, substrate surface parameters, and processing time is of key importance. The conditions investigated include deposition temperature, deposition pressure, SEG thickness, processing time, seed window area, distance between seed windows (local seed window density), and feed composition. The yield is found to improve with higher deposition temperatures, higher HCl feed flows, shorter processing times, higher Cl/H feed ratios, and lower Si/Cl feed ratios. The seed window area and distance between seed windows do not appear to affect the yield at the conditions studied. Growth rate uniformity is observed to improve with lower pressure and temperature, longer processing times, lower HCl feed concentrations, higher Si/Cl feed ratios, and lower Cl/H feed ratios. The implications of these observations for production planning and control of such facilities are discussed.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116713802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transport mechanism in borophosphosilicate glass passivation 硼磷硅酸盐玻璃钝化的输运机理

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559729

A. Achari

引用次数: 0

Designed experiments to analyze the solder joint quality output of a SMD remanufacturing system 设计实验分析SMD再制造系统的焊点质量输出

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559780

I. Fidan, R. Kraft, L. Ruff, S. Derby

引用次数: 4

Moldability improvements in thin quad flat packages (TQFPs) 薄型四平面封装(tqfp)的可塑性改进

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559741

S. Downey, D. Hagen, M. Lim, R. Ibrahim, K. Anuar, U. Malik

{"title":"Moldability improvements in thin quad flat packages (TQFPs)","authors":"S. Downey, D. Hagen, M. Lim, R. Ibrahim, K. Anuar, U. Malik","doi":"10.1109/IEMT.1996.559741","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559741","url":null,"abstract":"Experience has shown that in thin packages (20/spl times/20/spl times/1.4 mm), molding defects occur somewhat more frequently with large devices (12.7/spl times/12.7 mm), and devices molded in the die-down configuration. For these unique conditions, the mold compound flow front advanced slowly over the top surface of the die and rapidly over the back of the die exposed by the X-flag leadframe design. The most frequent defect observed in evaluations of die-up and die-down molding was exposed silicon after molding, caused by the uneven mold compound flow. To develop a robust molding process window, designed experiments were used to evaluate leadframe downset, mold gate design, molding compound, and molding parameters. Results showed that the leadframe downset was the most significant variable to improve moldability, and a deeper downset produced the best results. The molding process was optimized with two molding compounds, and the manufacturing process window is robust over a large variety of device sizes in both die-up and die-down molding configurations. All 112 lead and 144 lead packages from this line are qualified at JEDEC Level 1 for moisture sensitivity.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Developing an underfill process for dense flip chip applications 开发用于密集倒装芯片应用的下填充工艺

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559676

W. Leong

引用次数: 12

Application for ball grid array package by using high heat resistant substrate (BN300) 高耐热基板(BN300)在球栅阵列封装中的应用

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559684

A. Hagimura, K. Shima, K. Asahina, H. Sakuraba, K. Fujita, J. Tanaka

引用次数: 0