Developing an underfill process for dense flip chip applications

Abstract

HP's current generation workstation processor uses flip chip on ceramic technology to help achieve increased clock speeds and higher I/O count. Due to the large die size, underfill is needed to improve the fatigue life of the flip chip solder connections. The processor package offers limited access for dispensing the underfill, and places limits on excess flow on top of and around the die. An underfill process was developed for the processor that consists of depositing the underfill material in multiple passes. A series of experiments were performed to characterize the material properties, flow, and dispense equipment, and to optimize the cycle time. This paper presents the different experiments and a methodology for combining the results to specify a process. The results of this work can be applied to develop an underfill process for similar applications involving large flip chip die with limited dispensing access.