Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium最新文献_第6页

Developing an underfill process for dense flip chip applications 开发用于密集倒装芯片应用的下填充工艺

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559676

W. Leong

引用次数: 12

Microfilled via: an enabling technology for high density high performance high volume BGA substrates 微填充通孔:高密度、高性能、高容量BGA基板的使能技术

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559683

S. Chiang, J. Lan, B. Shepherd, P.Y.F. Wu

{"title":"Microfilled via: an enabling technology for high density high performance high volume BGA substrates","authors":"S. Chiang, J. Lan, B. Shepherd, P.Y.F. Wu","doi":"10.1109/IEMT.1996.559683","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559683","url":null,"abstract":"Microfilled Via (MfVia) is an enabling technology on which a superior and economical BGA substrate manufacturing is based. The main technology feature is a new method of creating a micro via by substituting the traditional costly drilling and plating process with a mass photoimageable via hole creation and stencil hole filling process. Via holes are later covered by copper through a foil lamination process to create a flat surface. Besides a dramatic reduction in the manufacturing cost, the new process also provides the following advantages: (1) True pad on via, (2) Superior Cu to photoimageable dielectric adhesion due to the lamination process, (3) High density outer layer process as the extra Cu plating on the outer layer is eliminated, (4) Low cost blind and buried via due to the sequential layer buildup and photo imaged vias. This high density via technology allows easy implementation of high pin-count substrates, even with the current generation line and spacing rule, such as 0.004\"/0.004\". This paper discusses the manufacturing, characterization and reliability of a BGA package manufactured using the microfilled via technology.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126507021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Measuring customer satisfaction for an R&D organization 测量一个研发组织的客户满意度

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559752

B. H. Fetz

引用次数: 2

Application for ball grid array package by using high heat resistant substrate (BN300) 高耐热基板(BN300)在球栅阵列封装中的应用

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559684

A. Hagimura, K. Shima, K. Asahina, H. Sakuraba, K. Fujita, J. Tanaka

引用次数: 0

A self-tuning EWMA controller utilizing artificial neural network function approximation techniques 利用人工神经网络函数逼近技术的自整定EWMA控制器

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559755

T. Smith, D. Boning

引用次数: 70

A multiple model approach to process control in electronics manufacturing 电子制造过程控制的多模型方法

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559787

A. Krauss, E. Kamen

引用次数: 2

Inner lead bonding for a resin molded chip size package 树脂模制芯片尺寸封装的内引线粘合

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559770

M. Nagasawa, S. Tanagawa, N. Yoshio, K. Igarashi, H. Yada

{"title":"Inner lead bonding for a resin molded chip size package","authors":"M. Nagasawa, S. Tanagawa, N. Yoshio, K. Igarashi, H. Yada","doi":"10.1109/IEMT.1996.559770","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559770","url":null,"abstract":"The present study investigated methods for bonding between semiconductor bonding pads and the metal bumps of a film carrier developed for use in chip-size packages (CSP). The structure of the film carrier is that of a copper circuit bearing a layer of insulating polyimide (PI) on both sides and connecting on one side with the exposed bumps, which in turn connect with the bonding pads. The bumps either have a copper core with a gold surface, or are all gold. In the first stage of the experiment, in which basic data were gathered, the ability of the bumps to bond via gang-bonding with the aluminum of the silicon chip was tested, using bumps with gold-plating of different thicknesses to give exposed heights of 10, 30 and 50 /spl mu/m. Bump height is a decisive factor in the peeling strength of the bonding site; satisfactory results were not achieved with low bumps of 10 /spl mu/m height. In the second stage, a method was sought which would help minimize production cost by ensuring successful bonding even with bumps of only 10 /spl mu/m height. The three following methods were tested and found effective: (1) inserting a convex frame immediately beneath the film carrier on the side opposite the bumps; (2) using a film carrier containing a layer of thermoplastic material immediately beneath the bumps; and (3) undertaking scrubbing during the initial bonding phase.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126702570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Life-cycle assessment of electronics manufacturing processes 电子制造过程的生命周期评估

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559740

T. Graedel

引用次数: 4

The NVESD microfactory: a new approach to infrared focal plane array manufacturing [HgCdTe] NVESD微工厂:红外焦平面阵列制造的新方法[HgCdTe]

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559731

J. Dinan, J. Benson, A. Cornfeld, M. Martinka, J.N. Johnson, J. Bratton, P. Taylor, B. Johs, P. He, S. Pittal, J. Woollam

引用次数: 3

Determining safety stock for semiconductor manufacturing 确定半导体制造的安全库存

Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium Pub Date : 1996-10-14 DOI: 10.1109/IEMT.1996.559749

Yi-Feng Hung

{"title":"Determining safety stock for semiconductor manufacturing","authors":"Yi-Feng Hung","doi":"10.1109/IEMT.1996.559749","DOIUrl":"https://doi.org/10.1109/IEMT.1996.559749","url":null,"abstract":"Semiconductor manufacturing requires many process steps performed by highly unreliable equipment. Such unreliability causes the means and variances of its cycle times to be generally larger than those of other industries. In addition, it makes the yields uncertain. While making the order quotation and calculating production plan, the safety stock must be used to guard against the uncertainty of the manufacturing processes to increase the on-time-delivery ratio and to provide better customer services. The randomness of cycle times and yields are the two major sources of the output uncertainty. Formerly, Hung [1991] proposed a method capable of obtaining the output lot distribution at a particular time on the planning horizon. The distribution could be obtained by using the production rate and the cycle time distribution which are readily available from the manufacturing database. However, the method does not adequately consider the yield uncertainty. While extending that method, this paper employs a simple variance calculation formula to incorporate the yield uncertainty when computing the variance of total good die output. After calculating this variance for a particular product at a particular time, the necessary safety stock for that die type at that time can be obtained.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127640524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2