树脂模制芯片尺寸封装的内引线粘合

M. Nagasawa, S. Tanagawa, N. Yoshio, K. Igarashi, H. Yada
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引用次数: 0

摘要

本研究研究了用于芯片尺寸封装(CSP)的半导体键合垫和薄膜载体的金属凸起之间的键合方法。薄膜载体的结构是铜电路的结构,其两侧有一层绝缘聚酰亚胺(PI),并在一侧与暴露的凸起连接,凸起又与键合垫连接。这些凸起要么有一个铜核,表面是金的,要么都是金的。在实验的第一阶段,收集了基本数据,测试了凸点与硅芯片铝的键合能力,使用不同厚度的镀金凸点,给出10、30和50 /spl mu/m的暴露高度。凹凸高度是影响粘接部位剥离强度的决定性因素;10 /亩/米高的低凸起效果不理想。在第二阶段,研究人员寻找一种方法,确保即使只有10 /spl mu/m高度的凸起也能成功粘合,从而帮助降低生产成本。测试了以下三种方法,发现效果良好:(1)在凸点对面的薄膜载体正下方插入凸框;(2)在凸起的正下方使用含有热塑性材料层的薄膜载体;(3)在初始粘合阶段进行擦洗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Inner lead bonding for a resin molded chip size package
The present study investigated methods for bonding between semiconductor bonding pads and the metal bumps of a film carrier developed for use in chip-size packages (CSP). The structure of the film carrier is that of a copper circuit bearing a layer of insulating polyimide (PI) on both sides and connecting on one side with the exposed bumps, which in turn connect with the bonding pads. The bumps either have a copper core with a gold surface, or are all gold. In the first stage of the experiment, in which basic data were gathered, the ability of the bumps to bond via gang-bonding with the aluminum of the silicon chip was tested, using bumps with gold-plating of different thicknesses to give exposed heights of 10, 30 and 50 /spl mu/m. Bump height is a decisive factor in the peeling strength of the bonding site; satisfactory results were not achieved with low bumps of 10 /spl mu/m height. In the second stage, a method was sought which would help minimize production cost by ensuring successful bonding even with bumps of only 10 /spl mu/m height. The three following methods were tested and found effective: (1) inserting a convex frame immediately beneath the film carrier on the side opposite the bumps; (2) using a film carrier containing a layer of thermoplastic material immediately beneath the bumps; and (3) undertaking scrubbing during the initial bonding phase.
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