M. Nagasawa, S. Tanagawa, N. Yoshio, K. Igarashi, H. Yada
{"title":"Inner lead bonding for a resin molded chip size package","authors":"M. Nagasawa, S. Tanagawa, N. Yoshio, K. Igarashi, H. Yada","doi":"10.1109/IEMT.1996.559770","DOIUrl":null,"url":null,"abstract":"The present study investigated methods for bonding between semiconductor bonding pads and the metal bumps of a film carrier developed for use in chip-size packages (CSP). The structure of the film carrier is that of a copper circuit bearing a layer of insulating polyimide (PI) on both sides and connecting on one side with the exposed bumps, which in turn connect with the bonding pads. The bumps either have a copper core with a gold surface, or are all gold. In the first stage of the experiment, in which basic data were gathered, the ability of the bumps to bond via gang-bonding with the aluminum of the silicon chip was tested, using bumps with gold-plating of different thicknesses to give exposed heights of 10, 30 and 50 /spl mu/m. Bump height is a decisive factor in the peeling strength of the bonding site; satisfactory results were not achieved with low bumps of 10 /spl mu/m height. In the second stage, a method was sought which would help minimize production cost by ensuring successful bonding even with bumps of only 10 /spl mu/m height. The three following methods were tested and found effective: (1) inserting a convex frame immediately beneath the film carrier on the side opposite the bumps; (2) using a film carrier containing a layer of thermoplastic material immediately beneath the bumps; and (3) undertaking scrubbing during the initial bonding phase.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"417 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The present study investigated methods for bonding between semiconductor bonding pads and the metal bumps of a film carrier developed for use in chip-size packages (CSP). The structure of the film carrier is that of a copper circuit bearing a layer of insulating polyimide (PI) on both sides and connecting on one side with the exposed bumps, which in turn connect with the bonding pads. The bumps either have a copper core with a gold surface, or are all gold. In the first stage of the experiment, in which basic data were gathered, the ability of the bumps to bond via gang-bonding with the aluminum of the silicon chip was tested, using bumps with gold-plating of different thicknesses to give exposed heights of 10, 30 and 50 /spl mu/m. Bump height is a decisive factor in the peeling strength of the bonding site; satisfactory results were not achieved with low bumps of 10 /spl mu/m height. In the second stage, a method was sought which would help minimize production cost by ensuring successful bonding even with bumps of only 10 /spl mu/m height. The three following methods were tested and found effective: (1) inserting a convex frame immediately beneath the film carrier on the side opposite the bumps; (2) using a film carrier containing a layer of thermoplastic material immediately beneath the bumps; and (3) undertaking scrubbing during the initial bonding phase.