{"title":"用于增强SMT和裸片组装应用的高复杂性PCB","authors":"S. Ehrler, R. Mayer, W. Olbrich, M. Roesch","doi":"10.1109/IEMT.1996.559718","DOIUrl":null,"url":null,"abstract":"New build-up technologies are necessary to meet the demands of future PC-boards. In this paper the DYCOstrate and PERL technologies are presented which use plasma etching for hole generation. These technologies offer advantages such as higher routing density, layer count reduction and lower production cost. Process flows are explained and possible constructions and design rules are presented. Electrical performance and reliability investigations have also been considered.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High complexity PCB's for enhanced SMT and bare chip assembly applications\",\"authors\":\"S. Ehrler, R. Mayer, W. Olbrich, M. Roesch\",\"doi\":\"10.1109/IEMT.1996.559718\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New build-up technologies are necessary to meet the demands of future PC-boards. In this paper the DYCOstrate and PERL technologies are presented which use plasma etching for hole generation. These technologies offer advantages such as higher routing density, layer count reduction and lower production cost. Process flows are explained and possible constructions and design rules are presented. Electrical performance and reliability investigations have also been considered.\",\"PeriodicalId\":177653,\"journal\":{\"name\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1996.559718\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High complexity PCB's for enhanced SMT and bare chip assembly applications
New build-up technologies are necessary to meet the demands of future PC-boards. In this paper the DYCOstrate and PERL technologies are presented which use plasma etching for hole generation. These technologies offer advantages such as higher routing density, layer count reduction and lower production cost. Process flows are explained and possible constructions and design rules are presented. Electrical performance and reliability investigations have also been considered.