C. Takubo, N. Hirano, K. Doi, H. Tazawa, E. Hosomi, Y. Hiruta
{"title":"芯片级封装用共晶焊料倒装技术","authors":"C. Takubo, N. Hirano, K. Doi, H. Tazawa, E. Hosomi, Y. Hiruta","doi":"10.1109/IEMT.1996.559794","DOIUrl":null,"url":null,"abstract":"Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the electrodes, a strong self-alignment effect and a low melting point. So, it is quite suitable for a chip assembly onto the plastic substrate as well as the ceramic substrate. An electroplating method has been developed for the formation of the eutectic solder bumps. The barrier metals has been selected as Ti/Ni/Pd for higher barrier effect. The flip chip interconnection process has been also developed. The various kinds of the reliability of the interconnection portion were investigated using the test vehicle of the ceramic and plastic substrate. The results of the test confirmed the reliable fabrication of the CSP using the eutectic solder flip chip technology.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Eutectic solder flip chip technology for chip scale package\",\"authors\":\"C. Takubo, N. Hirano, K. Doi, H. Tazawa, E. Hosomi, Y. Hiruta\",\"doi\":\"10.1109/IEMT.1996.559794\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the electrodes, a strong self-alignment effect and a low melting point. So, it is quite suitable for a chip assembly onto the plastic substrate as well as the ceramic substrate. An electroplating method has been developed for the formation of the eutectic solder bumps. The barrier metals has been selected as Ti/Ni/Pd for higher barrier effect. The flip chip interconnection process has been also developed. The various kinds of the reliability of the interconnection portion were investigated using the test vehicle of the ceramic and plastic substrate. The results of the test confirmed the reliable fabrication of the CSP using the eutectic solder flip chip technology.\",\"PeriodicalId\":177653,\"journal\":{\"name\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1996.559794\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Eutectic solder flip chip technology for chip scale package
Chip Scale Package (CSP) has been developed by applying the flip chip technology with the eutectic Sn/Pb solder bumps. The package size is only 1 mm larger than the chip size. The eutectic solder has advantages such as a good wettability to the electrodes, a strong self-alignment effect and a low melting point. So, it is quite suitable for a chip assembly onto the plastic substrate as well as the ceramic substrate. An electroplating method has been developed for the formation of the eutectic solder bumps. The barrier metals has been selected as Ti/Ni/Pd for higher barrier effect. The flip chip interconnection process has been also developed. The various kinds of the reliability of the interconnection portion were investigated using the test vehicle of the ceramic and plastic substrate. The results of the test confirmed the reliable fabrication of the CSP using the eutectic solder flip chip technology.