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IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)最新文献

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Triangle impulse response (TIR) calculation for lossy transmission line simulation 有耗传输线仿真中的三角形脉冲响应(TIR)计算
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967657
T. Zhou, Zhaoqing Chen, W. Becker, S. Dvorak, J. Prince
{"title":"Triangle impulse response (TIR) calculation for lossy transmission line simulation","authors":"T. Zhou, Zhaoqing Chen, W. Becker, S. Dvorak, J. Prince","doi":"10.1109/EPEP.2001.967657","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967657","url":null,"abstract":"Triangle-Impulse-Responses (TIR) are accurately calculated using an inverse Laplace transform algorithm. Frequency dependent transmission line parameters, i.e., R, L, G, and C, are used due to the skin effect and the frequency dependent electrical properties of the substrate material. The calculated TIR can be further used to carry out time domain simulations for a large number of lossy transmission lines.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122675405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits 高速互连电路非线性仿真的全局多级约简技术
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967659
P. Gunupudi, R. Khazaka, A. Dounavis, M. Nakhla, R. Achar
{"title":"Global multi-level reduction technique for nonlinear simulation of high-speed interconnect circuits","authors":"P. Gunupudi, R. Khazaka, A. Dounavis, M. Nakhla, R. Achar","doi":"10.1109/EPEP.2001.967659","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967659","url":null,"abstract":"Presents two approaches for simulation of large interconnect networks with linear/nonlinear terminations. The first approach is suitable in forming macromodels of interconnect networks in order to use them repeatedly in different configurations. The second approach is a nonlinear time-domain circuit reduction technique that reduces the whole interconnect network including the nonlinear/linear terminations. This method is independent of the number of ports in the system.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of via-induced parallel-plate resonances in a printed circuit board 印刷电路板中经孔诱导平行板共振的表征
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967612
M. Iwanami, S. Hoshino
{"title":"Characterization of via-induced parallel-plate resonances in a printed circuit board","authors":"M. Iwanami, S. Hoshino","doi":"10.1109/EPEP.2001.967612","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967612","url":null,"abstract":"This paper describes the fundamental characteristics of parallel-plate resonances which are induced by the via penetrating a parallel-plate in a multilayer printed circuit board (PCB). From the results of experiments and simulations, the origin of the strong resonance peak in the |S/sub 21/| characteristic is discussed. It is shown that the strong resonance peak may result from the correspondence between the parallel resonance frequencies in the input impedance of the parallel-plate and in that of the signal trace with the exception of the via.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132202700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Recent advances in reduced-order modeling of complex interconnects 复杂互连的降阶建模研究进展
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967655
S. Grivet-Talocia, I. Maio, F. Canavero
{"title":"Recent advances in reduced-order modeling of complex interconnects","authors":"S. Grivet-Talocia, I. Maio, F. Canavero","doi":"10.1109/EPEP.2001.967655","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967655","url":null,"abstract":"This paper addresses some important issues related to reduced-order modeling of complex interconnects. Two different but complementary directions are investigated. On one hand, multiport interconnect structures with possibly complex geometry are analyzed by means of model order reduction from transient scattering responses. On the other hand, some recent advances on stable and robust treatment of transmission lines with arbitrary frequency-dependent parameters are illustrated. Both modeling strategies lead to the automatic generation of a SPICE-ready equivalent circuit for system-level simulation.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125727913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Behavioral modeling of digital IC input and output ports 数字集成电路输入输出端口的行为建模
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967675
I. Stievano, Z. Chen, Dale Becker, F. Canavero, G. Katopis, I. Maio
{"title":"Behavioral modeling of digital IC input and output ports","authors":"I. Stievano, Z. Chen, Dale Becker, F. Canavero, G. Katopis, I. Maio","doi":"10.1109/EPEP.2001.967675","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967675","url":null,"abstract":"This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to the characterization of actual devices.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
An approach to measuring power supply impedance of microprocessors 一种测量微处理器电源阻抗的方法
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967648
G. Taylor, C. Deutschle, T. Arabi, B. Owens
{"title":"An approach to measuring power supply impedance of microprocessors","authors":"G. Taylor, C. Deutschle, T. Arabi, B. Owens","doi":"10.1109/EPEP.2001.967648","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967648","url":null,"abstract":"A technique to calculate the relative on die power supply impedance of high power CMOS integrated circuits as a function of frequency is described. This approach uses the power supply current variation that is normally present in a microprocessor to stimulate the supply network, varying the clock rate of the processor in order to obtain multiple measurements. Using this technique the power supply impedance vs. frequency of a 0.18 /spl mu/m microprocessor was measured and compared to a simple lumped circuit model.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117011347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SI and design considerations for Gbps PCBs in communication systems 通信系统中Gbps pcb的SI和设计考虑
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967665
Z. Mu, K. Willis
{"title":"SI and design considerations for Gbps PCBs in communication systems","authors":"Z. Mu, K. Willis","doi":"10.1109/EPEP.2001.967665","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967665","url":null,"abstract":"This paper covers the board level signal integrity issues at Gbps rates, impact of pre-emphasis, interconnect design considerations, and plane configuration techniques for power delivery. Pre-defined rules can be drawn from the discussion to guide high speed board designs.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116984483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Accurate closed-form expressions for the frequency-dependent line parameters of coupled on-chip interconnects on silicon substrate 硅衬底上耦合片上互连频率相关线路参数的精确封闭表达式
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967676
Hai Lan, Amy, A. Weisshaar
{"title":"Accurate closed-form expressions for the frequency-dependent line parameters of coupled on-chip interconnects on silicon substrate","authors":"Hai Lan, Amy, A. Weisshaar","doi":"10.1109/EPEP.2001.967676","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967676","url":null,"abstract":"Accurate closed-form expressions for the frequency-dependent [R], [L], [G], [C] line parameters of coupled on-chip interconnects on lossy silicon substrate are presented. The closed-form expressions for the frequency-dependent series impedance parameters are obtained using a complex image method. The frequency-dependent shunt admittance parameters are expressed using high- and low-frequency asymptotic static solutions. The proposed closed-from expressions are shown to be in good agreement with both quasi-static and full-wave electromagnetic solutions.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Effective decoupling radius of decoupling capacitor 去耦电容的有效去耦半径
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967663
Huabo Chen, J. Fang, Weimin Shi
{"title":"Effective decoupling radius of decoupling capacitor","authors":"Huabo Chen, J. Fang, Weimin Shi","doi":"10.1109/EPEP.2001.967663","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967663","url":null,"abstract":"Decoupling capacitors on packages and printed circuit boards are often essential to reduce voltage fluctuations and maintain power and signal integrity. This paper presents a measure for the evaluation of effectiveness of decoupling capacitors placed on package or board structures.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
New efficient method of modeling electronics packages with power and ground planes 具有电源和地平面的电子封装建模的一种新的有效方法
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI: 10.1109/EPEP.2001.967654
Weimin Shi, J. Fang
{"title":"New efficient method of modeling electronics packages with power and ground planes","authors":"Weimin Shi, J. Fang","doi":"10.1109/EPEP.2001.967654","DOIUrl":"https://doi.org/10.1109/EPEP.2001.967654","url":null,"abstract":"This paper introduces a new efficient numerical technique for the computation of fields in electronics packages with power and ground planes. This full wave approach can be conveniently integrated with circuit solvers. Skin-effect loss from metal planes and dielectric loss, together with the non-total reflections from outer edges of planes, can be easily incorporated. A special computation scheme was developed for handling vias between metal planes. Very good correlation has been achieved on printed-circuit test boards up to several GHz.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124464293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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