An approach to measuring power supply impedance of microprocessors

Abstract

A technique to calculate the relative on die power supply impedance of high power CMOS integrated circuits as a function of frequency is described. This approach uses the power supply current variation that is normally present in a microprocessor to stimulate the supply network, varying the clock rate of the processor in order to obtain multiple measurements. Using this technique the power supply impedance vs. frequency of a 0.18 /spl mu/m microprocessor was measured and compared to a simple lumped circuit model.