ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献_第6页

A 2.17-pJ/b 5b-Response Attack-Resistant Strong PUF with Enhanced Statistical Performance 一个2.17-pJ/b 5b响应抗攻击、增强统计性能的强PUF

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911472

Kunyang Liu, Gen Li, Zihan Fu, Xuanzhen Wang, H. Shinohara

引用次数: 2

Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security 逻辑嵌入式物理不可克隆功能，用于低面积和设计成本物联网安全的可合成和无外设实现

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911394

Seonho Kim, C. Im, Jongmin Lee, Soyoun Jeong, Jaerok Kim, Yoonmyung Lee

引用次数: 0

A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps 基于重叠条纹推理的4.6-8.3 TOPS/W 1.2-4.9 TOPS cnn计算成像处理器，实现4K超高清30fps

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911515

Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang

{"title":"A 4.6-8.3 TOPS/W 1.2-4.9 TOPS CNN-based Computational Imaging Processor with Overlapped Stripe Inference Achieving 4K Ultra-HD 30fps","authors":"Yu-Chun Ding, Kai-Pin Lin, Chi-Wen Weng, Li-Wei Wang, Huan-Ching Wang, Chun-Yeh Lin, Yong-Tai Chen, Chao-Tsung Huang","doi":"10.1109/ESSCIRC55480.2022.9911515","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911515","url":null,"abstract":"In this paper, we present an energy-efficient acceler-ator chip which supports high-quality CNN-based computational imaging applications at 4K UItra-UD 30fps. To address the huge requirement of DRAM bandwidth and computing energy, an overlapped stripe inference flow and a structure-sparse $text{CONV}3mathrm{x}3$ engine are proposed respectively. The former reduces DRAM bandwidth to 0.81-1.74 GB/s when supporting high-quality CNN inference with 16 to 29 layers at 4K UItra-UD 30fps. The latter reduces computing complexity by 40% without noticeable quality degradation, e.g. 0.02-0.03 dB of PSNR drop. More specifically, it uses only 4.9 intrinsic TOPS of computing capability at 200 MHz to approach the quality of dense models which demand up to 8.2 TOPS. In addition, a coarse-grained reconfigurable datapath is designed to support diverse Applications including super-resolution, denoising, and style transfer with high hardware efficiency. Fabricated in 40nm CMOS, this chip achieves 4.6-8.3 TOP/W of energy efficiency for high-quality computational imaging applications. We also implement an FPGA-aided system to demonstrate real-time processing for the diverse applications supported by the fabricated chip.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129276906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A $1.8mumathrm{W} 5.5$ mm3 ADC-less Neural Implant SoC utilizing 13.2pJ/Sample Time-domain Bi-phasic Quasi-static Brain Communication with Direct Analog to Time Conversion 基于13.2pJ/Sample的时域双相准静态脑通信和直接模拟时间转换的无adc神经植入芯片(1.8mu mathm {W} 5.5$ mm3

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911420

Baibhab Chatterjee, K. G. Kumar, Shulan Xiao, Gourab Barik, K. Jayant, Shreyas Sen

{"title":"A $1.8mumathrm{W} 5.5$ mm3 ADC-less Neural Implant SoC utilizing 13.2pJ/Sample Time-domain Bi-phasic Quasi-static Brain Communication with Direct Analog to Time Conversion","authors":"Baibhab Chatterjee, K. G. Kumar, Shulan Xiao, Gourab Barik, K. Jayant, Shreyas Sen","doi":"10.1109/ESSCIRC55480.2022.9911420","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911420","url":null,"abstract":"Untethered miniaturized wireless neural sensor nodes with data transmission and energy harvesting capabilities call for circuit and system-level innovations to enable ultra-low energy deep implants for brain-machine interfaces. Realizing that the energy and size constraints of a neural implant motivate highly asymmetric system design (a small, low-power sensor and transmitter at the implant, with a relatively higher power receiver at a body-worn hub), we present Time-Domain Bi-Phasic Quasi-static Brain Communication (TD-BPQBC), offloading the burden of analog to digital conversion (ADC) and digital signal processing (DSP) to the receiver. The input analog signal is converted to time-domain pulse-width modulated (PWM) waveforms, and transmitted using the recently developed BPQBC method for reducing communication power in implants. The overall SoC consumes only $1.8 mumathrm{W}$ power while sensing and communicating at 800kSps. The transmitter energy efficiency is only 1.1pJ/b, which is >30X better than the state-of-the-art, enabling a fully-electrical, energy-harvested, and connected in-brain sensor/stimulator node.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122597049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Full-Duplex Wireless for (Joint-) Communication and Sensing 全双工无线(联合)通信和传感

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911367

Hany Abolmagd, Raghav Subbaraman, Dinesh Bharadia, S. Shekhar

引用次数: 1

A scalable $64times 64$ pixels monolithic HV-CMOS sensor for hadron therapy with 1ns time stamping capability and in-pixel ADC 一种可扩展的64 × 64像素单片HV-CMOS传感器，用于强子治疗，具有1ns时间戳能力和像素内ADC

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911225

N. Massari, A. D'Andragora, M. Perenzoni, Andrey Selijak, Carlos Chavez Barajas, Alan Taylor, J. Taylor, G. Casse, J. Pettingell, Ignacio Di Biase

引用次数: 0

Improvement of FTJ on-current by work function engineering for massive parallel neuromorphic computing 面向大规模并行神经形态计算的功函数工程改进FTJ导通电流

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911392

S. Lancaster, Q. Duong, E. Covi, T. Mikolajick, S. Slesazeck

引用次数: 1

A Portable CMOS-based MRI System with 67×67×83 µm3Image Resolution 具有67×67×83µm3图像分辨率的便携式cmos MRI系统

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911344

Daniel Krüger, Aoyang Zhang, Henry Hinton, V. M. Arnal, Yi-Qiao Song, Yiqiao Tang, Ka-Meng Lei, J. Anders, D. Ham

引用次数: 3

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm 1.23 ghz 16kb可编程sram通用处理65nm加速器

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911440

Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae-sun Seo, Deliang Fan

引用次数: 3

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec 基于28nm CMOS技术的具有自适应DFE和变间隔3倍过采样CDR的50 Mb/s全HBC TRX，用于75 cm体通道以0.75周期/秒移动

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911296

Jaehyun Ko, Iksu Jang, Chanho Kim, Jihoon Park, Changjae Moon, Sooeun Lee, Byungsub Kim

{"title":"A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec","authors":"Jaehyun Ko, Iksu Jang, Chanho Kim, Jihoon Park, Changjae Moon, Sooeun Lee, Byungsub Kim","doi":"10.1109/ESSCIRC55480.2022.9911296","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911296","url":null,"abstract":"This paper reports a 50 Mb/s full human body communication (HBC) transceiver (TRX) that communicates through a 75 cm body channel moving at speed of 0.75 cycle/sec. For the first time, adaptive decision feedback equalization (DFE) and a clock and data recovery (CDR) were integrated in a HBC TRX to adapt to a moving body channel in real time. In the proposed design, the transmitter (TX) consists of inverter-based driver that transmits non-return-to-zero (NRZ) signal to human body. The receiver (RX) utilized a 10-tap adaptive DFE to compensate for time-varying inter symbol interferences (ISIs) of moving body channel. Also, for clock synchronization, variable-interval 3x oversampling CDR (VI-3x-CDR) was adopted to overcome wide and asymmetric data-dependent jitter (DDJ). A test chip was fabricated in 28 nm CMOS technology. Compared with the prior arts that were measured with moving body channel, the data rate and the area were improved by 10x and 3x, respectively.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1