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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)最新文献

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A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration −247.1 dB FoM，−77.9dBc参考杂散环振荡器注入锁定时钟乘法器，带多相校准
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911362
Yeonggeun Song, Kyoung-Soo Ha, H. Ko, Min-Seong Choo, D. Jeong
{"title":"A −247.1 dB FoM, −77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration","authors":"Yeonggeun Song, Kyoung-Soo Ha, H. Ko, Min-Seong Choo, D. Jeong","doi":"10.1109/ESSCIRC55480.2022.9911362","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911362","url":null,"abstract":"This paper presents a ring-oscillator (RO)-based injection-locked clock multiplier (ILCM) with a new background calibration technique that utilizes a multi-phase generation capability of the RO. By detecting phase changes before and after the injection pulse, both a frequency error and an injection path offset are calibrated. The frequency calibrator operates at the injection rate with high bandwidth, which contributes to further suppressing flicker noise of the RO and producing much lower RMS jitter. The path offset calibrator operating at the pulse-gating rate makes the ILCM converge to the state with a minimum reference spur. For a low-power implementation, a sub-sampling bang-bang phase detector is employed for each calibration loop and all of the loops operate at the reference clock rate. Fabricated in 28-nm CMOS, the proposed ILCM achieves 143.6-fs RMS jitter with a −77.9-dBc reference spur and consumes 9.4 mW at the 4.8-GHz operation, which translates to a FoM of −247.1 dB.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference (ESSCIRC): On Line PROCEEDINGS ESSCIRC 2022 - IEEE第48届欧洲固态电路会议(ESSCIRC):在线会议记录
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/esscirc55480.2022.9911371
{"title":"ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference (ESSCIRC): On Line PROCEEDINGS","authors":"","doi":"10.1109/esscirc55480.2022.9911371","DOIUrl":"https://doi.org/10.1109/esscirc55480.2022.9911371","url":null,"abstract":"","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"6 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131623316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Next “Automation Age”: How Semiconductor Technologies Are Changing Industrial Systems and Applications 下一个“自动化时代”:半导体技术如何改变工业系统和应用
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911230
D. Arrigo, C. Adragna, V. Marano, Rachela Pozzi, Fulvio Pulicelli, F. Pulvirenti
{"title":"The Next “Automation Age”: How Semiconductor Technologies Are Changing Industrial Systems and Applications","authors":"D. Arrigo, C. Adragna, V. Marano, Rachela Pozzi, Fulvio Pulicelli, F. Pulvirenti","doi":"10.1109/ESSCIRC55480.2022.9911230","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911230","url":null,"abstract":"A profound transformation is making the industrial world more technically advanced and sustainable: the “Next Automation Age.” The changes are driven by demand for increased safety for both personnel and equipment in factories, higher levels of intelligence in processes, and greater flexibility and efficiency. Newer semiconductor technologies like wide-bandgap silicon carbide and gallium nitride, combined with advanced digital control architectures, can deliver significantly higher power densities and conversion efficiency than conventional silicon technologies. Advances in smart power BCD process technologies, with embedded phase-change memories, can facilitate transitions from analog to digital control improving power conversion and motor-control applications. Embedded on-chip, galvanic isolation extends or supersedes earlier-generation system-level protections with superior intrinsic safety and robustness. At the same time, it protects users from electric shocks while delivering exceptional power and high-speed data transfer rates across isolated barriers. These are just some of the innovations emerging from an industrial electronics sector striving to meet the smart industry trends of the current and foreseeable sustainable future.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications 用于智能电源应用的90纳米BCD扩展温度范围ePCM存储器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911379
M. Carissimi, C. Auricchio, E. Calvetti, L. Capecchi, Mattia Luigi Torres, Stefano Zanchi, P. Gupta, R. Zurla, A. Cabrini, D. Gallinari, F. Disegni, M. Borghi, E. Palumbo, A. Redaelli, M. Pasotti
{"title":"An Extended Temperature Range ePCM Memory in 90-nm BCD for Smart Power Applications","authors":"M. Carissimi, C. Auricchio, E. Calvetti, L. Capecchi, Mattia Luigi Torres, Stefano Zanchi, P. Gupta, R. Zurla, A. Cabrini, D. Gallinari, F. Disegni, M. Borghi, E. Palumbo, A. Redaelli, M. Pasotti","doi":"10.1109/ESSCIRC55480.2022.9911379","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911379","url":null,"abstract":"This paper presents a temperature-robust embedded Phase-Change Memory (ePCM) with high cycling capability able to meet all the stringent specifications coming from the automotive environment and, more specifically, the used phase-change material (based on Ge-rich GST alloy) has been tuned to fit power ICs constraints. In order, to cope with the −40 °C to 175 °C operation requirements, a temperature-compensated write algorithm was conceived and specific circuits were added to render the statistical distribution of programming pulses equal at any temperature as it is required to obtain a uniform ageing of the cells thus ensuring an higher reliability after 100k cycling. Programming operation was optimized thanks to an improved program load that has been designed to compensate for the expected large power supply variations. Experimental characterization demonstrated a 16 ns access time over the whole temperature range.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"103 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132365055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers 一种用于5G NR无线供电中继收发器的CMOS全波开关整流器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911328
Sena Kato, Keito Yuasa, Michihiro Ide, A. Shirane, K. Okada
{"title":"A CMOS Full-Wave Switching Rectifier with Frequency Up-Down Conversion for 5G NR Wirelessly-Powered Relay Transceivers","authors":"Sena Kato, Keito Yuasa, Michihiro Ide, A. Shirane, K. Okada","doi":"10.1109/ESSCIRC55480.2022.9911328","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911328","url":null,"abstract":"This paper presents a CMOS full-wave switching rectifier capable of mixer operation. The proposed CMOS switching rectifier allows DC power generation and frequency conversion without a power supply. The proposed CMOS switching rectifier using a center-tapped balun produces DC power with 25% efficiency, while at the same time providing frequency up-conversion with -18.9 dB and down-conversion with -11.9 dB. The size of the chip is 0.286 mm2, and four chips are mounted on the phased-array antenna board. The board can be used as a wirelessly powered relay module, and the module can be driven without an external power supply. The measured EVM values are -27.4dB for Tx mode and -27.5dB for Rx mode with a 400-MHz 64QAM OFDMA-mode signal (5G NR, MCS 17).","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115109929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages 91.6%的峰值效率时域控制单电感三输出升压转换器，具有±7.5至±12V双极输出电压
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911293
Peng Cao, Danzhu Lu, Jiawei Xu, Xiaoyang Zeng, Zhiliang Hong
{"title":"A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages","authors":"Peng Cao, Danzhu Lu, Jiawei Xu, Xiaoyang Zeng, Zhiliang Hong","doi":"10.1109/ESSCIRC55480.2022.9911293","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911293","url":null,"abstract":"This paper presents a time-domain-controlled (TDC) single-inductor triple-output (SITO) step-up converter with enhanced load transient response. The proposed converter can convert 2.7 to 5V input voltage into a pair of bipolar high output voltages ranging from ±7.5 to ±12V and a 5V positive output voltage with a maximum output power of 9.6W. By using the time-domain controller and an ADC-assisted fast settling loop, the converter exhibits a fast transient response with low undershoot/overshoot voltages. The proposed converter was fabricated in a 180nm BCD process. With a 2MHz switching frequency, the converter achieves a peak conversion efficiency of 91.6% at an output power of 2.25W.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"1 8‐9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration 6GS/s 8通道CIC SAR TI-ADC与神经网络校准
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911287
Evelyn Ware, Justin M. Correll, Seungjong Lee, Michael J. Flynn
{"title":"6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration","authors":"Evelyn Ware, Justin M. Correll, Seungjong Lee, Michael J. Flynn","doi":"10.1109/ESSCIRC55480.2022.9911287","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911287","url":null,"abstract":"In this paper we introduce an area efficient time-interleaved charge-injection-cell SAR ADC. The prototype TI-ADC interleaves 8 CIC SAR channels for a sampling rate of 6Gs/s and a compact area of 0.0060Smm2. A neural network calibration algorithm corrects multiple error sources in the time-interleaved ADC. The neural calibration method effectively improves the average measured ENOB of the TI-ADC from 4.1 bits to 5.49 bits.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW 一个2GHz 2位连续时间Delta Sigma ADC，带2GHz斩波器，在153kHz时实现12nV/sqrt(Hz) 1/f噪声，在30MHz BW时实现-104.7dBc的THD
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911312
P. Cenci, H. Brekelmans, Shagun Bajoria, M. Ganzerli, Bernard Burdiek, R. Rutten, Yihan Gao, M. Bolatkale, Paul Swinkels, L. Breems
{"title":"A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW","authors":"P. Cenci, H. Brekelmans, Shagun Bajoria, M. Ganzerli, Bernard Burdiek, R. Rutten, Yihan Gao, M. Bolatkale, Paul Swinkels, L. Breems","doi":"10.1109/ESSCIRC55480.2022.9911312","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911312","url":null,"abstract":"This paper presents a 2GHz 2-bit continuous-time Delta Sigma ADC employing a 2GHz chopper to achieve low 1/f noise while maintaining high spectral purity over a 30MHz bandwidth. The proposed ADC achieves 12n V/(sqrt(Hz)) noise density at 153kHz, 78.5dB SNDR, -104.7dBc THD and better than 122dBFS SFDR (excluding HDx) in 30MHz BW. It is fabricated in a 28nm CMOS process consuming 61.4mW.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121457544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Integrated Optical Transceiver Circuit for Power Delivery and Bi-directional Data Communication in a Medical Catheter Device 用于医用导管设备供电和双向数据通信的集成光收发器电路
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911483
A. Frank, J. Anders, J. Burghartz, Bart Kootte, J. Schleipen, P.T. Jutte
{"title":"An Integrated Optical Transceiver Circuit for Power Delivery and Bi-directional Data Communication in a Medical Catheter Device","authors":"A. Frank, J. Anders, J. Burghartz, Bart Kootte, J. Schleipen, P.T. Jutte","doi":"10.1109/ESSCIRC55480.2022.9911483","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911483","url":null,"abstract":"In this paper*, the realization of an optical transceiver circuit (OTC) integrated into a customized catheter system is presented. The electronics at the distal end of the catheter is located far away from the external bed-side unit and is connected by an optical link to control its functions. By means of light only, the optical link simultaneously delivers power and establishes a bi-directional data communication. The optical link consists of just a few components, i.e. a multi-mode fiber, a blue LED, an external unit and the optical transceiver circuit. The LED is located at the catheter tip and is used by the OTC to operate as an optical transceiver and energy harvester. Several circuit blocks are integrated into the OTC, to provide a regulated voltage of 1.8 V at a maximum current of 2.1 mA. The OTC establishes a communication with a speed of up to 15.6 kBits/s for receiving and 1.35 MBits/s for transmitting data. Because of the small area and only less components to set up the link at the sensor side, the optical link is very suitable for application to the catheter system presented in this paper. The concept can also be applied to other biomedical or industrial sensor systems, where conventional approaches, using electrical wiring, are unpractical.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126162043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR mueller - m<e:1> CDR中带假锁感知的56gb /s PAM4收发器
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI: 10.1109/ESSCIRC55480.2022.9911409
F. Tachibana, H. Ngo, Go Urakawa, Takashi Toi, M. Ashida, Y. Tsubouchi, M. Nozawa, J. Wadatsumi, H. Kobayashi, J. Deguchi
{"title":"A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR","authors":"F. Tachibana, H. Ngo, Go Urakawa, Takashi Toi, M. Ashida, Y. Tsubouchi, M. Nozawa, J. Wadatsumi, H. Kobayashi, J. Deguchi","doi":"10.1109/ESSCIRC55480.2022.9911409","DOIUrl":"https://doi.org/10.1109/ESSCIRC55480.2022.9911409","url":null,"abstract":"This paper presents a 56-Gb/s PAM4 transceiver using an ADC-based RX with a false-lock-aware locking scheme for Mueller-Müller (MM) CDR. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.","PeriodicalId":168466,"journal":{"name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127334058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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