P. Cenci, H. Brekelmans, Shagun Bajoria, M. Ganzerli, Bernard Burdiek, R. Rutten, Yihan Gao, M. Bolatkale, Paul Swinkels, L. Breems
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A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW
This paper presents a 2GHz 2-bit continuous-time Delta Sigma ADC employing a 2GHz chopper to achieve low 1/f noise while maintaining high spectral purity over a 30MHz bandwidth. The proposed ADC achieves 12n V/(sqrt(Hz)) noise density at 153kHz, 78.5dB SNDR, -104.7dBc THD and better than 122dBFS SFDR (excluding HDx) in 30MHz BW. It is fabricated in a 28nm CMOS process consuming 61.4mW.
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