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1989 Proceedings of the IEEE Custom Integrated Circuits Conference最新文献

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A 30 MHz low-noise CMOS preamplifier for disk drive heads 用于磁盘驱动器磁头的30 MHz低噪声CMOS前置放大器
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56704
T. Pan, A. Abidi
{"title":"A 30 MHz low-noise CMOS preamplifier for disk drive heads","authors":"T. Pan, A. Abidi","doi":"10.1109/CICC.1989.56704","DOIUrl":"https://doi.org/10.1109/CICC.1989.56704","url":null,"abstract":"Data stored as magnetic flux reversals on a hard disk are read by an inductive head in close proximity to the disk, across which voltage signals of 0.1-1 mV are induced by the flux. These analog signals must be amplified before they are converted to logic levels by a decision circuit. A read-head preamplifier specially designed to be driven by an inductive source is used for this purpose. In a modern disk-drive subsystem, this amplifier must be wideband (>30 MHz), have a voltage gain of at least 100, and have low input noise (<2 nV/√Hz). The authors report on the first such amplifier fabricated in a 3-μm CMOS process. Some of the unique advantages offered by a CMOS design are highlighted, and its performance in a disk subsystem is compared with that of the industry standard bipolar preamplifier","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116841562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure 一种改进并行结构的15 ns 32倍32位CMOS乘法器
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56842
M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka
{"title":"A 15 ns 32&times;32-bit CMOS multiplier with an improved parallel structure","authors":"M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka","doi":"10.1109/CICC.1989.56842","DOIUrl":"https://doi.org/10.1109/CICC.1989.56842","url":null,"abstract":"A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116839539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Physics-based bipolar transistor model for low-temperature circuit simulation 基于物理的双极晶体管低温电路仿真模型
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56719
J. Liou, J. Yuan
{"title":"Physics-based bipolar transistor model for low-temperature circuit simulation","authors":"J. Liou, J. Yuan","doi":"10.1109/CICC.1989.56719","DOIUrl":"https://doi.org/10.1109/CICC.1989.56719","url":null,"abstract":"A comprehensive bipolar transistor model based on the Gummel-Poon model for low-temperature circuit simulation is presented. Low-temperature physical properties such as doping-dependent dielectric permittivity, temperature-dependent free-carrier mobility and intrinsic carrier density, and deionization of impurity dopants are included in the model. Consequently, the model does not require temperature-fitting parameters as does the Gummel-Poon model. Comparisons of the present model with the Gummel-Poon model, with experimental data, and with PISCES two-dimensional device simulation are included","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121884748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A custom processor for use in a parallel computer system 一种用于并行计算机系统的自定义处理器
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56728
D. Wilde
{"title":"A custom processor for use in a parallel computer system","authors":"D. Wilde","doi":"10.1109/CICC.1989.56728","DOIUrl":"https://doi.org/10.1109/CICC.1989.56728","url":null,"abstract":"A 440000-transistor, full-custom CMOS processor that is used as the basis of a parallel computer system is described. The primary design goal was to produce a processor that performed roughly an order of magnitude faster than its predecessor. The author discusses the chip-level architecture of the processor, comparing it to the original design, and shows what was done architecturally to increase the performance by an order of magnitude","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123247477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computing DC large change sensitivities 计算直流大变化灵敏度
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56804
D. Divekar, H. Daseking, R. Apte
{"title":"Computing DC large change sensitivities","authors":"D. Divekar, H. Daseking, R. Apte","doi":"10.1109/CICC.1989.56804","DOIUrl":"https://doi.org/10.1109/CICC.1989.56804","url":null,"abstract":"Large change sensitivities are needed in many situations since parameters are subjected to variations that are not small. The authors have implemented three different methods in SPICE3 for computing DC large change sensitivities. The incremental approach is observed to give speed improvements of more than an order of magnitude over the direct approach","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121741405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS low distortion sample and hold circuit for audio D/A converter 用于音频D/A转换器的CMOS低失真采样和保持电路
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56701
N. Sugawa, T. Ikarashi, K. Kuwana, T. Kawakami, A. Kimitsuka, T. Iida
{"title":"CMOS low distortion sample and hold circuit for audio D/A converter","authors":"N. Sugawa, T. Ikarashi, K. Kuwana, T. Kawakami, A. Kimitsuka, T. Iida","doi":"10.1109/CICC.1989.56701","DOIUrl":"https://doi.org/10.1109/CICC.1989.56701","url":null,"abstract":"A CMOS low distortion sample and hold circuit with total harmonic distortion of 0.01% for audio D/A (digital-to-analog) convertor has been developed, using a novel circuit architecture and high-speed operational amplifier. As an application of this technology to the audio field, an audio signal delay processing LSI with high-resolution A/D and D/A converters has been realized. The LSI has been fabricated using a 1.5-μm CMOS process and a die size of 18.5 mm2","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"30 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120914051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An expert system to assist in diagnosis of failures on VLSI memories 一个专家系统，以协助诊断故障的超大规模集成电路存储器
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56838
T. Viacroze, M. Lequeux
{"title":"An expert system to assist in diagnosis of failures on VLSI memories","authors":"T. Viacroze, M. Lequeux","doi":"10.1109/CICC.1989.56838","DOIUrl":"https://doi.org/10.1109/CICC.1989.56838","url":null,"abstract":"A description is given of an expert system that helps diagnose failures on VLSI memories. The expert system is intended to be used in the fields of quality assurance and failure analysis. After a discussion of the problem and the definition of the project, the different databases used and the architecture of the expert system are described. Then, the strategy of the system, which depends on the kind of failure diagnosed after a first-level analysis, is explained. Current developments are discussed that are intended to improve the capability of the expert system and depth of diagnosis","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124007648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator 可编程，四通道，128采样，40毫秒/秒模拟三元相关器
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56828
S. C. Munroe, D. R. Arsenault, K. E. Thompson, A. Lattes
{"title":"Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator","authors":"S. C. Munroe, D. R. Arsenault, K. E. Thompson, A. Lattes","doi":"10.1109/CICC.1989.56828","DOIUrl":"https://doi.org/10.1109/CICC.1989.56828","url":null,"abstract":"The authors designed, fabricated, and tested a four-channel, analog-ternary charge-coupled device (CCD) correlator that extends the state of the art in several important areas. In addition to a sampling rate up to 40 Ms/s, dynamic range of 66 dB, and nonlinearity below -50 dB, the device exhibits a level of integration and user-friendliness not previously available. The correlator is intended for use in communications and radar systems where pseudonoise codes are used","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
GaAs MESFET digital integrated circuits fabricated with low temperature buffer technology 采用低温缓冲技术制备GaAs MESFET数字集成电路
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56782
M. Delaney, C. Chou, L. Larson, J. Jensen, D. Deakin, A. Brown, W. Hooper, M. Thompson, L. McCray, S. Rosenbaum
{"title":"GaAs MESFET digital integrated circuits fabricated with low temperature buffer technology","authors":"M. Delaney, C. Chou, L. Larson, J. Jensen, D. Deakin, A. Brown, W. Hooper, M. Thompson, L. McCray, S. Rosenbaum","doi":"10.1109/CICC.1989.56782","DOIUrl":"https://doi.org/10.1109/CICC.1989.56782","url":null,"abstract":"High-performance digital integrated circuits have been fabricated with low-temperature buffer GaAs MESFET technology. The materials structure eliminates side-gating and light sensitivity, and improves FET performance. Individual transistors with a 0.2-μm gate length have a transconductance gm of 600 mS/mm and an extrapolated cutoff frequency fT of 80 GHz. Static SCFL frequency dividers fabricated in this technology exhibit a maximum clock rate of 22 GHz","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127925437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dominant pole(s)/zero(s) analysis for analog circuit design 模拟电路设计的主导极/零分析
1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI: 10.1109/CICC.1989.56802
L. Pillage, C. Wolff, R. Rohrer
{"title":"Dominant pole(s)/zero(s) analysis for analog circuit design","authors":"L. Pillage, C. Wolff, R. Rohrer","doi":"10.1109/CICC.1989.56802","DOIUrl":"https://doi.org/10.1109/CICC.1989.56802","url":null,"abstract":"A prototype frequency-domain simulator that models the nth-order circuit by a lower order q-model has been developed. It combines results equivalent to hand analysis with variable order numerical pole-zero approximation. The dominant poles and zeros, including those that are complex or repeated, are found efficiently on recursive DC analysis of the circuit. In addition, the effect of the variation of element values on the pole locations can be obtained at an incremental cost in CPU time","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128339959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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