A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure

Abstract

A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation