M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka
{"title":"一种改进并行结构的15 ns 32倍32位CMOS乘法器","authors":"M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka","doi":"10.1109/CICC.1989.56842","DOIUrl":null,"url":null,"abstract":"A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure\",\"authors\":\"M. Nagamatsu, Sumio Tanaka, J. Mori, T. Noguchi, K. Hatanaka\",\"doi\":\"10.1109/CICC.1989.56842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"122 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 15 ns 32×32-bit CMOS multiplier with an improved parallel structure
A 32-bit×32-bit parallel multiplier with an improved parallel structure has been fabricated by 0.8-μm CMOS triple-level-metal interconnection technology. A unit adder that can sum four partial products concurrently has been developed. It enhances the parallelism of multiplier. The chip contains 27704 transistors with 2.68×2.71-mm2 die area. The multiplication time is 15 ns at 5-V power supply. The power dissipation is 277 mW at 10-MHz operation