2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)最新文献_第2页

Performance Analysis and Impact of Manufacturing Tolerances of multi-layers package substrate for 5G mmWave Antenna in Package/Module (AiP/AiM) 5G毫米波天线封装/模块(AiP/AiM)多层封装基板性能分析及制造公差影响

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013302

Cheng-Yu Ho, Sheng-Chi Hsieh, Hong-Sheng Huang, Chia-Ching Chu, Chen-Chao Wang

引用次数: 0

Automated Analysis of AFM Data of High-Density Cu Pad for Fine Pitch Wafer-to-Wafer (W2W) and Chip-to-Wafer (C2W) Hybrid Bonding 高密度铜衬垫的AFM数据自动分析用于小间距晶对晶(W2W)和芯片对晶(C2W)混合键合

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013174

Jiakai Chen, Yong Chyn Ng, D. K. Mishra, K. Chui

引用次数: 0

High Performance Multi-Chip Leadframe Package with Internal Connection 具有内部连接的高性能多芯片引线框架封装

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013282

DaeYoung Park, HyeongIl Jeon, G. Kim, JiYeon Yang, KwangSoo Sang, B. Kim, JinYoung Khim

引用次数: 0

Numerical fluidic-chemical multi-physics simulation of a mass production model for electroless plating of fine-pitch interconnections in a microchannel for chip packaging applications 用于芯片封装的微通道细间距互连化学镀量产模型的流体化学多物理场数值模拟

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013221

S. J. Gräfner, J.H. Huang, P. Shih, V. Renganathan, P. Kung, Y.A. Chen, C.H. Huang, C. Chen, C. Kao

{"title":"Numerical fluidic-chemical multi-physics simulation of a mass production model for electroless plating of fine-pitch interconnections in a microchannel for chip packaging applications","authors":"S. J. Gräfner, J.H. Huang, P. Shih, V. Renganathan, P. Kung, Y.A. Chen, C.H. Huang, C. Chen, C. Kao","doi":"10.1109/EPTC56328.2022.10013221","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013221","url":null,"abstract":"Current chip packaging technologies for fine-pitch interconnections require high heat and pressure which could lead to failures on the surrounding delicate parts in the scaling-down process. By using electroless plating instead, these limitations could be avoided which already has been demonstrated in various experiments. However, the transition from experiments in the laboratory to the industrial fabrication has to face various challenges. A numerical multi-physics model to investigate the fluidic-chemical aspects while scaling-down the geometry for a possible mass production is developed. By the usage of this model, possible limitations, theoretical requirements and optimizations on the packaging system can be estimated and investigated. The results show that the pressure gradient of the model follows Darcy's law for porous medium. Furthermore, pillar couplings with gap usually have a non-uniform grow behavior. This non-uniformity can be optimized by applying a dome-shaped pillar-tip. Moreover, the convectional flux is in most of the samples of the domain dominant. Only by approaching the reactions surface, diffusion becomes a relevant part of the mass transport. The investigation of the Cu-ion concentration gradient shows that more Cu-ions are consumed while scaling down.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127429606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aero Acoustic MEMS Microphone Integration in Ultra-Thin and Flexible Substrate 航空声学MEMS麦克风在超薄柔性基板上的集成

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013281

K. Erbacher, Joao Alves Marques, Malte von Krshiwoblozki, Lixiang Wu, H. Ngo, M. Schneider-Ramelow

引用次数: 2

Digital Lithography for Advanced Packaging and Heterogenous Integration 先进封装和异构集成的数字光刻技术

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013141

B. Dielacher, S. Schmölzer, T. Matthias, B. Považay, F. Bögelsack, R. Holly, T. Zenger, T. Uhrmann, B. Thallner

引用次数: 1

Lithography process optimization to realize RDL layers on high topography wafers for heterogeneous integration 优化光刻工艺，在高形貌晶圆上实现RDL层异质集成

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013306

S. Merugu, S. A. Sek, Navab Singh

引用次数: 1

Chip-to-Wafer Hybrid Bonding for high performance 2.5D applications 用于高性能2.5D应用的芯片到晶圆混合键合

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013161

S. Chong, Ismael Cereno Daniel, V. N. Sekhar, S. Lim, V. Srinivas

引用次数: 0

Numerical Simulations to Assist Chip-to-Wafer Hybrid Bonding Process Development 数值模拟，以协助芯片到晶圆混合键合工艺的发展

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013143

Sasi Kumar Tippabhotla, L. Ji, C. Choong

{"title":"Numerical Simulations to Assist Chip-to-Wafer Hybrid Bonding Process Development","authors":"Sasi Kumar Tippabhotla, L. Ji, C. Choong","doi":"10.1109/EPTC56328.2022.10013143","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013143","url":null,"abstract":"Development of chip to wafer hybrid bonding (C2W-HB) process is essential to achieve direct bonding of fine pitch (≤ 10 μm) Cu interconnects for heterogeneous integration. As the polymer mechanical behavior is more complex, C2W-HB with direct bonding of Cu/polymer-dielectrics requires significant experimental efforts, resources, and time to design the test vehicles and formulate the process recipe for high quality and yield. In this work, numerical simulations are performed to evaluate the bonding progression for a special case where SiO2 dielectric is used for the bottom wafer and polymer dielectric is used for the top dies. As these two materials are quite different in their thermomechanical behaviour, bonding of the Cu/Cu interfaces depends on the relative expansion/contraction of the surrounding SiO2 (bottom wafer) and dielectric polymer (top die) interface. Our simulations help to elucidate the mechanics at the bonding interface and explain the reasons for the bonding failures observed in the experimental runs. The simulation results show that Cu pad dishing is not suitable for this configuration and protrusion of Cu pads is required to get a successful Cu/Cu direct bonding.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-line test structures for yield improvement in MEMS/NEMS device 用于提高MEMS/NEMS器件成品率的在线测试结构

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013245

J. Sharma, Yul Koh, Sagnik Ghosh, Han Xuan Wong, L. Joshua

{"title":"In-line test structures for yield improvement in MEMS/NEMS device","authors":"J. Sharma, Yul Koh, Sagnik Ghosh, Han Xuan Wong, L. Joshua","doi":"10.1109/EPTC56328.2022.10013245","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013245","url":null,"abstract":"The integration of novel process flows for the fabrication of microelectromechanical system (MEMS) and nanoelectromechanical system (NEMS) devices invariably requires an initial round of short loops to qualify the critical process steps prior to full device fabrication. This paper presents some of the initial short loop based in-line qualification results obtained during the fabrication of zero-power wake-up acceleration switches fabricated on silicon-on-insulator (SOI) wafers with 1µm buried oxide (BOX) for a range of active silicon thicknesses. Narrow trench openings in the silicon device layer is a common requirements in the fabrication of MEMS and NEMS devices in SOI. Isolation across narrow gaps was verified in-line through electrical measurements, corroborated by cross-sectional inspections from scanning electron micrographs (SEM). Similarly, the release of MEMS structures by vapor hydrofluoric acid (VHF) was verified by in-line infrared (IR) inspection metrology tool after removing the metal from the test structures to be inspected. These test structures for in-line metrology inspection help shorten the fabrication time and improve the yield of the final fabricated device.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0