{"title":"Lithography process optimization to realize RDL layers on high topography wafers for heterogeneous integration","authors":"S. Merugu, S. A. Sek, Navab Singh","doi":"10.1109/EPTC56328.2022.10013306","DOIUrl":null,"url":null,"abstract":"This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC56328.2022.10013306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work demonstrates wafer-level thin film encapsulation (TFE) [1], [2] of a radio-frequency microelectromechanical systems (RF MEMS) device with rerouting of contacts and pads for flip-chip compatibility to a much smaller CMOS chip. RF MEMS devices are a key market driver for growth in the MEMS industry. This article enunciates the optimization of lithography steps in defining redistribution layers (RDL) and opening bond pads on high topography RFMEMS wafer to reduce RC delay and match bond pad locations for Heterogeneous integration of MEMS with ASIC.