2012 4th Asia Symposium on Quality Electronic Design (ASQED)最新文献_第5页

Effects of Mn nanoparticles on wettability and intermetallic compounds in between Sn-3.8Ag-0.7Cu and Cu substrate during multiple reflow 多次回流过程中Mn纳米颗粒对Sn-3.8Ag-0.7Cu与Cu衬底润湿性及金属间化合物的影响

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320519

Koh Kai Xiang, A. Haseeb, M. M. Arafat, G. Yingxin

引用次数: 9

A new design methodology of networks on chip 一种新的片上网络设计方法

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320467

A. Mahdoum

引用次数: 4

Delay-line based embedded memory access time measurement: Circuit, implementation and characterization techniques 基于延迟线的嵌入式存储器访问时间测量:电路、实现和表征技术

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320512

Moo Kit Lee, Wei Khoon Teng, R. Krishnasamy, W. T. Ng

{"title":"Delay-line based embedded memory access time measurement: Circuit, implementation and characterization techniques","authors":"Moo Kit Lee, Wei Khoon Teng, R. Krishnasamy, W. T. Ng","doi":"10.1109/ACQED.2012.6320512","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320512","url":null,"abstract":"Embedded memory access time is an important parameter that determines the performance of the memory. To accurately characterize the embedded memory access time across Process, Voltage and Temperature (PVT) variation is always a challenge. In order to get more accurate memory access time data across PVT, the proper implementation of embedded memory access time measurement circuitry and characterization flow is required. This paper presents the circuits, design implementation and characterization methodology for embedded memory access time. We discuss two methods of memory access time measurement circuits, followed by comparing the advantages and disadvantages between them. The result from simulation versus silicon characterization is presented. The first method is Mux-Based Memory Access Time Measurement Circuit (MATC), using simple controller logic to write and read to the memory, plus a Mux and Digital Test Point (DTP) for external measurement. The measurement method is fully off-chip. The second method is Delay-Line Based MATC. It requires more complex circuitry, but the access time measurement is on-chip.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121684427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A low-cost capacitive relative humidity sensor for food moisture monitoring application 一种用于食品湿度监测的低成本电容式相对湿度传感器

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320483

Bo Wang, M. Law, A. Bermak

引用次数: 7

Signaling analysis of inter-chip I/O package routing for Multi-Chip Package 多芯片封装中芯片间I/O包路由的信令分析

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320509

K. Yong, W. Song, B. E. Cheah, M. F. Ain

{"title":"Signaling analysis of inter-chip I/O package routing for Multi-Chip Package","authors":"K. Yong, W. Song, B. E. Cheah, M. F. Ain","doi":"10.1109/ACQED.2012.6320509","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320509","url":null,"abstract":"Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs [1]. However, the high density interchip I/O routing within package presents unique signaling challenges when coupled with high operating data rate. This paper focuses on the signaling analysis of the inter-chip I/O package routing between silicon devices in MCP. In this study, high level signal quality and eye margin sensitivity were evaluated from 2.5GHz up-to 7.5GHz. The microwave effect is found dominating the transmission line component that resulted in signal quality deteriorations. Key limiting factors such as crosstalk coupling effects, signal reflections and frequency dependent losses that caused signal quality degradations were identified and categorized according to the operating frequency and channel length for future MCP design considerations.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Power awareness for multi-voltage island X-clock tree construction with double-via insertion 带双通孔插入的多电压岛型x时钟树结构的电源感知

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320495

Chia-Chun Tsai, Trong-Yen Lee

引用次数: 1

Structural package and board design approach for System-on-Chip power delivery analysis 片上系统功耗分析的结构封装和电路板设计方法

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320508

Wai Ling Lee, Li Chuang Quek

{"title":"Structural package and board design approach for System-on-Chip power delivery analysis","authors":"Wai Ling Lee, Li Chuang Quek","doi":"10.1109/ACQED.2012.6320508","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320508","url":null,"abstract":"With the increasing complexity of circuit design, CPU and chipset electrical design target has changed and continue to be more stringent. Power delivery design is getting more challenging to ensure no device functional failure in low power and low cost product. Therefore, platform power delivery engineer is playing an essential role in implementing robust electrical solution. Despite of all these, there is a hidden challenge as System-on-Chip power delivery engineer does not have platform design detail for instance package stack-up and number of layer as well as platform size to initiate power delivery design. This urges the team to transform from traditional passive power delivery working model to more proactive role. This paper presents structural approach of platform parasitic estimation at early product definition phase and production design cycle phase. Accurate estimation of platform parasitic is important to enable early product power delivery involvement and BGA (Ball Grid Array) reduction that could facilitate product cost saving. The correlation of the estimated result and the simulated result is presented and further discussed in the study.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Clock tree construction using gated clock cloning 利用门控时钟克隆构建时钟树

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320475

Wun-Han Chen, Hsin-Hung Chang, Jui-Hung Hung, T. Hsieh

引用次数: 5

Low-power and robust SRAM cells based on asymmetric FinFET structures 基于非对称FinFET结构的低功耗和鲁棒SRAM单元

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320473

B. Ebrahimi, R. Asadpour, A. Afzali-Kusha

{"title":"Low-power and robust SRAM cells based on asymmetric FinFET structures","authors":"B. Ebrahimi, R. Asadpour, A. Afzali-Kusha","doi":"10.1109/ACQED.2012.6320473","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320473","url":null,"abstract":"In this paper, we investigate the characteristics of low-power and robust SRAM cells based on asymmetric FinFET structures in a 32 nm technology. They are based on asymmetric source and drain structures and include Asymmetric Drain Spacer Extension (ADSE) and Asymmetric Doped Drain (ADD) FinFETs. The study includes two recently introduced 6-T SRAM cells based on these structures. In addition, we propose four transistor driverless (4-TDL) and loadless (4-TLL) SRAM cells based on these asymmetric structures. In the investigation, which compares the structures, the effect of different channel orientations is also considered. The results indicate that for 6-T, 4-TDL, and 4-TLL with different channel orientations asymmetric structures have higher read stabilities than the symmetric ones. In addition, the channel orientation (100) presents a higher read stability for 4-TLL while the channel orientation (110) gives rise to a better read stability for 6-T and 4-TDL. Asymmetric structures, however, have lower read currents where the ADSE structure leads to the least one. In terms of write operation, the asymmetric structures present better stability where 4-T cells outperform the 6-T cell. Finally, the results on static power shows that the ADD FinFET structure provides the lowest static power values due to a better DIBL control.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Decoupling capacitor placer algorithm with routing and area consideration in VLSI layout design VLSI版图设计中考虑布线和面积的去耦电容放料算法

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320489

Thomas Goh Fong Chee, Jonathan Ong Yoong Seang, Chun Keong Lee

引用次数: 0