2012 4th Asia Symposium on Quality Electronic Design (ASQED)最新文献

A 2.5–12.5Gbps interpolator-based clock and data recovery circuit for FPGA 基于2.5-12.5Gbps插补器的FPGA时钟和数据恢复电路

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320515

Lip-Kai Soh, Wai-Tat Wong

引用次数: 8

Fully synthesizable delay cell design for emulation environment 仿真环境下的全合成延迟单元设计

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320511

Tee Kok Khim, Lim Thiam Ern

{"title":"Fully synthesizable delay cell design for emulation environment","authors":"Tee Kok Khim, Lim Thiam Ern","doi":"10.1109/ACQED.2012.6320511","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320511","url":null,"abstract":"This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly dependent on the complexity of the design. Both of these designs use conventional clock synchronous flip flops and simple logic gates to construct emulation friendly delay cell modules. The first design was constructed to support asynchronous based inputs while the latter design is capable of supporting various types of clock signals. Both of these two proposed designs have two parameters settings. The first parameter is used to configure the multiplier value of intended delay while the second parameter is used to configure the width of the input and output ports. These designs also require a reference clock, reset signal and user input to be connected to their input ports as well. The output from these designs is a delayed version of the user input. Finally the functionality of these designs have been verified on both simulation and emulation platforms.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114136406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Solar Harvested energy prediction algorithm for wireless sensors 无线传感器太阳能收获能量预测算法

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320497

Muhammad Hassan, A. Bermak

引用次数: 38

A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps 一种提高CMOS运算放大器自动设计优化效率的偏置驱动方法

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320476

Yanan Cheng, L. Chan, Yen-Lung Chen, Yu-Ching Liao, C.N.J. Liu

{"title":"A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps","authors":"Yanan Cheng, L. Chan, Yen-Lung Chen, Yu-Ching Liao, C.N.J. Liu","doi":"10.1109/ACQED.2012.6320476","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320476","url":null,"abstract":"The equation-based analog design automation is getting popular in last decade to search the optimal solutions with good efficiency. However, due to the deep-submicron effects, significant modeling errors often exist in major transistor parameters like gds and gm. This often results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. Instead of building complex parameter models for gds and gm, this paper adopts the gm/Id design concept, which is an independent value to the device size, on equation-based optimization to solve the accuracy issue. Without the complex effects from W and L, the modeling accuracy of transistor parameters is significantly improved. No more iteration is required by using the proposed approach, which improves the efficiency as well as the accuracy. To the best of our knowledge, this is the first work that adopts the internal voltages instead of device sizes as the unknown variables to be solved. As demonstrated on several circuits with different objectives, both the accuracy and efficiency of circuit optimization can be improved significantly.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"22 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129037905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Impact on signal integrity of differential pair routing over split plane and voids 分割面和空隙上差分对布线信号完整性的影响

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320490

A. Omar Mukhtar, Y. Ahmad Jalaluddin, J. Kong, M.S. Aftanasar

引用次数: 2

A robust incremental power grid analyzer by macromodeling approach and Orthogonal Matching Pursuit 基于宏建模和正交匹配追踪的鲁棒增量电网分析仪

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320477

Yi-Hsuan Lee, Yu-Min Lee, L. Cheng, Yen-Tang Chang

引用次数: 3

0.5 V, 3 6µW Gm-C Butterworth low pass filter in 0.18µm CMOS process 0.5 V, 3.6µW Gm-C Butterworth低通滤波器，0.18µm CMOS工艺

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320480

V. M. Harishchandra, T. Laxminidhi

引用次数: 3

Soft-error hardened redundant triggered latch 软错误硬化冗余触发闩锁

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320514

H. K. Alidash, S. Sayedi, V. Oklobdzija

引用次数: 0

Effects of Sn concentration and current density on Sn-Bi electrodeposition in additive free plating bath 无添加剂镀液中Sn浓度和电流密度对Sn- bi电沉积的影响

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320517

Chiew Ying Heong, A. Haseeb, G. Yingxin, Lee Seen Fang

{"title":"Effects of Sn concentration and current density on Sn-Bi electrodeposition in additive free plating bath","authors":"Chiew Ying Heong, A. Haseeb, G. Yingxin, Lee Seen Fang","doi":"10.1109/ACQED.2012.6320517","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320517","url":null,"abstract":"Sn-Bi alloys were electroplated from sulphuric acid based plating baths containing tin sulfate (SnSO4) and bismuth nitrate (Bi(NO3)3). The electrochemical behavior of the plating bath was investigated by electrochemical studies. Potentiodynamic polarization curves of the plating bath revealed the large potential gap between the two elements. The effects of SnSO4 concentration and current density on the composition and morphology of the Sn-Bi electrodeposition were investigated. The surface morphology and composition of the Sn-Bi electrodeposited were investigated by scanning electron microscopic (SEM) coupled with energy dispersive X-ray (EDS) spectroscopic. The Sn content in the deposits increased with increasing of Sn content in the bath. Bi content was found to decrease with increasing current density because of the more noble deposition potential of Bi. The microstructure and surface morphology of the Sn-Bi electrodeposits become finer and smoother with increasing Sn content in bath but rougher and less compact when current density is increased. Sn-36.47 wt.% Bi alloy was fabricated from this additive free plating bath.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129566320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Formation of Sn-Bi alloys through sequential electrodeposition 序贯电沉积法制备Sn-Bi合金

2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320493

Lee Seen Fang, A. Haseeb, G. Yingxin

{"title":"Formation of Sn-Bi alloys through sequential electrodeposition","authors":"Lee Seen Fang, A. Haseeb, G. Yingxin","doi":"10.1109/ACQED.2012.6320493","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320493","url":null,"abstract":"The fabrication of near eutectic Sn-Bi alloy can be developed by reflowing a metal stack containing layers of Sn and Bi films. The Sn and Bi metal films are sequentially electroplated using two separate plating baths. Composition control of Sn-Bi alloy can be achieved by manipulating the thickness of constituent metal films. The thickness ratio of Sn to Bi is targeted to be approximately 0.97 to obtain the eutectic composition. Hence, the effect of thickness as a function of time is investigated. The thickness of electroplated layers increased with plating time but a more uniform thickness can be obtained from shorter plating periods. Methane sulphonate acid (MSA) based baths were fabricated for both Sn and Bi plating and the current density used is 20 mA/cm2 and 5 mA/cm2 respectively. Hydroquione (HQ) and gelatin were added into Sn plating solution bath as additives to improve the bath stability. The dual layer metal stack was reflowed at 170°C to enhance the interdiffusion between Sn and Bi layers. Field Emission Scanning Electron Microscope (FESEM) analyses coupled with Energy Disperse X-ray (EDX) analyses test have been performed to investigate the microstructure and composition of Sn-Bi alloy. Homogeneous microstructure of Sn-Bi alloy is obtained after reflow and near eutectic composition Sn- 54.6 wt.%Bi is achieved.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130248100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2