{"title":"An all-digital clock and data recovery circuit for spread spectrum clocking applications in 65nm CMOS technology","authors":"Ching-Che Chung, D. Sheng, Yang-Di Lin","doi":"10.1109/ACQED.2012.6320482","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320482","url":null,"abstract":"In this paper, an all-digital clock and data recovery (ADCDR) circuit is presented. The proposed ADCDR can recover the data stream sent by a transmitter with a spread spectrum clock generator (SSCG). The proposed adaptive gain control scheme can automatically adjust the phase tracking gain by counting the consecutive identical digits (CID), and the time-to-digital converter (TDC)-based fast phase compensation can quickly compensate for a large phase error. The proposed ADCDR can tolerate input peak-to-peak jitter up to 130ps at 480MHz with the down-spread 10% modulation. In addition, the bit error rate (BER) is less than 10-12 with 231-1 pseudo-random binary sequence (PRBS). The proposed ADCDR is implemented in a standard performance 65nm CMOS process with standard cells. The active area is 130μm × 100μm, and the power consumption is 1.13mW at 480MHz with the down-spread 10% modulation.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"392 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123364892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyoungrok Cho, Hyeong-Seok Na, Tae-Won Cho, Younggap You
{"title":"Analysis of system bus on SoC platform using TSV interconnection","authors":"Kyoungrok Cho, Hyeong-Seok Na, Tae-Won Cho, Younggap You","doi":"10.1109/ACQED.2012.6320506","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320506","url":null,"abstract":"This paper proposes a latency model for a multi-layer system on chip (SoC) structure employing through silicon vias (TSVs). TSVs are used to interconnect multiple SoC chips stacked to form a three-dimensional (3-D) structure. The proposed latency model has been used to estimate the system performance. The performance estimation reflects the number of IPs connected to the system bus, data throughput and the number of masters in the system. The maximum throughput calculation results can be used to find the appropriate number of chips to be stacked during the 3-D multi-layer SoC system design process.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125631928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The effect of higher order model decoupling capacitors in the design of a power delivery network","authors":"Li Wern Chew","doi":"10.1109/ACQED.2012.6320486","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320486","url":null,"abstract":"Decoupling capacitors are widely used in power delivery network (PDN) design to mitigate switching noise from the integrated circuit (IC). Besides, they also provide a low-impedance path to shunt the transient energy to ground at the IC source. Since a real capacitor includes both parasitic inductance and resistance associated with the interconnection and package of the capacitor resulting in an increase in impedance, adequate decoupling capacitances in a PDN design are essential. Often, a capacitor is represented with a higher order model (HOM) of resistance, inductance and capacitance in power delivery simulation. This paper presents the findings from an investigation into the PDN performance using various HOM decoupling capacitors of the same capacitance. The reasons for the different HOM values with the same capacitance include the form factor, manufacturing processes and the operating temperature of the capacitors. From the study, it was found that both the form factor and the differences in the capacitors manufacturing process can cause a significant difference in the impedance profile as well as the voltage droop whereas the operating temperature has a much less impact on the PDN performance.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115476767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simultaneous switching noise impact to signal eye diagram on high-speed I/O","authors":"S. R. Chan, F. Tan, R. Mohd-Mokhtar","doi":"10.1109/ACQED.2012.6320501","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320501","url":null,"abstract":"Simultaneous Switching Noise (SSN) is increasing with higher I/O data rate, resulting into more challenges in regulating supply voltage noise. SSN increases jitter in high-speed interface circuit and limits the performance of I/O. In order to reduce SSN effect to supply voltage droop, Power Distribution Network (PDN) has to be designed optimally. PDN design goal is to reduce the power supply noise going into I/O circuit. Engineering efforts are focused on packaging and board routing in order to control the impedance profile and supply voltage droop within the design specification. This paper discusses the next level of investigation, quantifying the effect of supply noise to the I/O transistor level circuit performance, specifically on Universal Serial Bus (USB) transmitter circuit. Output of the USB's transmitted signal is shown in eye diagram with the existence of supply noise throughout PDN. Results show that the USB transmitter circuit can sustain with higher supply noise drop than the targeted PDN design.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121571757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}