发布求助
文献互助 智能选刊 最新文献

2012 4th Asia Symposium on Quality Electronic Design (ASQED)最新文献

筛选
英文 中文
On regularity and integrated DFM metrics 关于规律性和综合DFM指标
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320503
K. Subramaniyan, P. Larsson-Edefors
{"title":"On regularity and integrated DFM metrics","authors":"K. Subramaniyan, P. Larsson-Edefors","doi":"10.1109/ACQED.2012.6320503","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320503","url":null,"abstract":"Transistor geometries are well into the nanometer regime, keeping with Moore's Law. With this scaling in geometry, problems not significant in the larger geometries have come to the fore. These problems, collectively termed variability, stem from second-order effects due to the small geometries themselves and engineering limitations in creating the small geometries. The engineering obstacles have a few solutions which are yet to be widely adopted due to cost limitations in deploying them. Addressing and mitigating variability due to second-order effects comes largely under the purview of device engineers and to a smaller extent, design practices. Passive layout measures that ease these manufacturing limitations by regularizing the different layout pitches have been explored in the past. However, the question of the best design practice to combat systematic variations is still open. In this work we explore considerations for the regular layout of the exclusive-OR gate, the half-adder and full-adder cells implemented with varying degrees of regularity. Tradeoffs like complete interconnect unidirectionality, and the inevitable introduction of vias are qualitatively analyzed and some factors affecting the analysis are presented. Finally, results from the Calibre Critical Feature Analysis (CFA) of the cells are used to evaluate the qualitative analysis.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115780647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effects of thiourea and gelatin on the electrodeposition of Sn-Ag solder alloy 硫脲和明胶对锡银焊料合金电沉积的影响
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320518
Lee Wei, A. Haseeb, G. Yingxin
{"title":"Effects of thiourea and gelatin on the electrodeposition of Sn-Ag solder alloy","authors":"Lee Wei, A. Haseeb, G. Yingxin","doi":"10.1109/ACQED.2012.6320518","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320518","url":null,"abstract":"Sulfuric acid based Sn-Ag plating baths were developed to study the individual as well as synergistic effects of thiourea (TU) and gelatin on the characteristics of Sn-Ag deposits. Electrochemical behavior of each bath was investigated by cathodic polarization studies. Results showed that the deposition potential gap of both elements was reduced by both additives, hence allowing co-deposition of Sn-Ag to occur. In this study, TU increases Ag composition and changes deposits microstructure. Low content of gelatin inhibits Ag deposition but high content of gelatin results in enhanced Ag deposition. Microstructure of deposits has been improved by the synergistic effects of these two additives. Near-eutectic composition of Sn-4.0 wt.% Ag is achieved with the aid of 2g/L of TU and 1g/L of gelatin at a current density of 10mA cm-2.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125180890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Robustness validation of integrated circuits and systems 集成电路和系统的鲁棒性验证
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320491
M. Barke, M. Kargel, W. Lu, F. Salfelder, L. Hedrich, M. Olbrich, M. Radetzki, Ulf Schlichtmann
{"title":"Robustness validation of integrated circuits and systems","authors":"M. Barke, M. Kargel, W. Lu, F. Salfelder, L. Hedrich, M. Olbrich, M. Radetzki, Ulf Schlichtmann","doi":"10.1109/ACQED.2012.6320491","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320491","url":null,"abstract":"Robust system design is becoming increasingly important, because of the ongoing miniaturization of integrated circuits, the increasing effects of aging mechanisms, and the effects of parasitic elements, both intrinsic and external. For safety reasons, particular emphasis is placed on robust system design in the automotive and aerospace sectors. Until now, the term robustness has been applied very intuitively and there has been no proper way to actually measure robustness. However, the complexity of contemporary systems makes it difficult to fulfill tight specifications. For this reason, robustness must be integrated into a partially automated design flow. In this paper, a new approach to robustness modeling is presented, in addition to new ways to quantify or assess the robustness of a design. To demonstrate the flexibility of the proposed approach, it is adapted and applied to several different scenarios. These include the robustness evaluation of digital circuits under aging effects, such as NBTI; the robustness modeling of analog and mixed signal circuits using affine arithmetic; and the robustness study of software algorithms on a high system level.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"18 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
NOC-based MPSoC design and implementation on FPGA: DCT application 基于noc的MPSoC设计与FPGA实现:DCT应用
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320516
O. Hammami, M. H. Jabbar
{"title":"NOC-based MPSoC design and implementation on FPGA: DCT application","authors":"O. Hammami, M. H. Jabbar","doi":"10.1109/ACQED.2012.6320516","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320516","url":null,"abstract":"The era of multiprocessor system-on-chip (MPSoC) has brought a new challenge for modern electronic systems. Communication between IP cores and other peripheral in the MPSoC environment is becoming critical which will affect the performance. Network-on-Chip (NoC) is a promising solution for MPSoC communication limitation. Several NoC studies have been reported over the years but only a few discussed about the actual hardware implementation. In this paper, we presented FPGA design and implementation of MPSoC system with NoC architectures in order to obtain its actual performance. A case study of Discrete Cosine Transform (DCT) using parallel programming is carried out to validate the design.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132234472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wideband LNA design for SDR radio using balanced amplifier topology 基于平衡放大器拓扑的SDR无线电宽带LNA设计
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320481
Anwar Faizd Osman, N. Noh
{"title":"Wideband LNA design for SDR radio using balanced amplifier topology","authors":"Anwar Faizd Osman, N. Noh","doi":"10.1109/ACQED.2012.6320481","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320481","url":null,"abstract":"This paper presents the design and development of a wideband low noise amplifier (LNA) suitable for Software Defined Radio (SDR) base station. The LNA design is based on the balanced amplifier topology, using the hybrid coupler and advanced GaAs E-PHEMPT transistor technology in order to produce a good wideband performance on all the critical parameters. By using the balanced amplifier design topology, the design yields excellent return loss, noise figure and linearity performance for the wideband application, and by utilizing the hybrid coupler in the balanced amplifier topology reduces the PCB size compared to normal balanced amplifier topology. The wideband LNA was designed on a PCB board with FR4 substrate and exhibits a small signal gain of 18 dB, noise figure of 1 dB, return loss (input and output) greater than 10 dB and IIP3 greater than 11 dBm across the wideband frequency range from 136-941 MHz (TIA-603C full frequency range), with a dual supply of 5V and total current consumptions of 120mA.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132110474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Low power AMOLED driving scheme based on reduced data supply voltage 基于降低数据供电电压的低功耗AMOLED驱动方案
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320479
E. Song, Hoon Jeong, Hyoungsik Nam
{"title":"Low power AMOLED driving scheme based on reduced data supply voltage","authors":"E. Song, Hoon Jeong, Hyoungsik Nam","doi":"10.1109/ACQED.2012.6320479","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320479","url":null,"abstract":"This paper demonstrates a new driving scheme which allows reducing the supply voltage of data drivers for low power active matrix organic light emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor (TFT) covers the same range as a conventional one by means of a level-shifting scheme, the low data supply scheme achieves the equivalent dynamic range of OLED currents. The normalized power consumptions have been kept at the lower level than 0.25.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128767883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Field-based parasitic capacitance models for 2D and 3D sub-45-nm interconnect 基于场的2D和3D sub- 45nm互连寄生电容模型
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320485
Aixi Zhang, Wei Zhao, Xiaoan Zhu, W. Deng, Jin He, Aixin Chen, M. Chan
{"title":"Field-based parasitic capacitance models for 2D and 3D sub-45-nm interconnect","authors":"Aixi Zhang, Wei Zhao, Xiaoan Zhu, W. Deng, Jin He, Aixin Chen, M. Chan","doi":"10.1109/ACQED.2012.6320485","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320485","url":null,"abstract":"In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error comparing with a traditional model fitting process. The new compact model has been verified with COMSOL simulations. It accurately predicts the capacitance for not only the nominal wire dimensions from the latest ITRS updates, but also for a wide range of other BEOL wire dimensions.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"18 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimization of routing architecture and performance for FPGA routing fabric FPGA路由结构和性能的优化
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320468
B. Tan
{"title":"Optimization of routing architecture and performance for FPGA routing fabric","authors":"B. Tan","doi":"10.1109/ACQED.2012.6320468","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320468","url":null,"abstract":"Being a critical highway between FPGA core IPs, the routing fabric components play an integral part in overall core performance. Optimizing the components in the routing fabric region is not a trivial task when considering the multitude of variable physical parameters involved especially the profound association with software programming and constantly changing process parameters. Common optimization algorithm would be discussed, incorporating propose multi-dimensional graphical method. Case study illustrates the potential of graphical method in identifying optimal component sizing and tradeoffs, aiding design and decision making in delivering the most optimal designs in routing fabric region. Supported by comprehensive graphical performance visualization, basic routing element architecture would also be discussed, developing expressions to promote faster optimization by narrowing down the region of interest; improving resource utilization on optimization.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114502566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Genetic algorithm-based optimization in 4th order Sallen Key high pass filter 基于遗传算法的四阶Sallen Key高通滤波器优化
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320496
K. L. Cheng, S. Neoh
{"title":"Genetic algorithm-based optimization in 4th order Sallen Key high pass filter","authors":"K. L. Cheng, S. Neoh","doi":"10.1109/ACQED.2012.6320496","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320496","url":null,"abstract":"Circuit designers often face difficulties and challenges to deal with the complex trade-offs of Analog IC design. Considering such complex trade-offs, optimization of circuit design often requires large amount of time and effort. This paper proposed a Genetic Algorithm (GA)-based optimization model for optimizing the design variables of a 4th order Sallen Key high pass filter. The aims of the design are to maximize the output gain, minimize the pass-band ripple, and achieve the targeted cut-off frequency. The GA is executed in conjunction with the LTSPICE circuit simulation system to assess the filter performance. Overall results satisfied the required design specifications.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Packaging performance of GaAs/InGaAs/InGaP collector-up HBTs as power amplifiers 作为功率放大器的GaAs/InGaAs/InGaP集电极HBTs封装性能
2012 4th Asia Symposium on Quality Electronic Design (ASQED) Pub Date : 2012-07-10 DOI: 10.1109/ACQED.2012.6320520
H. Tseng, W. Chu
{"title":"Packaging performance of GaAs/InGaAs/InGaP collector-up HBTs as power amplifiers","authors":"H. Tseng, W. Chu","doi":"10.1109/ACQED.2012.6320520","DOIUrl":"https://doi.org/10.1109/ACQED.2012.6320520","url":null,"abstract":"GaAs/InGaAs/InGaP collector-up heterojunction bipolar transistors (HBTs), with an effective thermal-dissipation packaging (TDP) configuration, have been developed. The TDP-implemented multi-finger collector-up HBT with a graded InGaAs base is demonstrated to achieve compelling high-speed and heat-removing performances. Extraordinarily, the TDP has a stronger influence on the p-n-p device than on the n-n-p device. The results show that the thermal resistance has been substantially decreased by 50%, and a power-added efficiency (PAE) more than 56% is obtained. Thermal performance for miniature power amplifiers in next-generation cellular phones can be greatly improved from our design.","PeriodicalId":161858,"journal":{"name":"2012 4th Asia Symposium on Quality Electronic Design (ASQED)","volume":"87 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120893767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信